公开(公告)号：US20240153856A1

公开(公告)日：2024-05-09

申请号：US18386003

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonghyun BAEK ,  Hyunsoo CHUNG ,  Dongok KWAK ,  Eunjeong IM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H10B80/00 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311

Abstract: A semiconductor package having a lower redistribution structure includes a redistribution insulation layer, a plurality of ball pads in the redistribution insulation layer apart from one another, a double via which includes a first active via and a dummy via located on at least one of the plurality of ball pads and apart from each other in the redistribution insulation layer, and a first active redistribution layer electrically connected to the first active via in the redistribution insulation layer, solder balls electrically connected to the plurality of ball pads under the lower redistribution structure, a first semiconductor chip on the lower redistribution structure and electrically connected to the first active via and the first active redistribution layer of the lower redistribution structure, and a molding layer molding the first semiconductor chip on the lower redistribution structure.

公开(公告)号：US20240250066A1

公开(公告)日：2024-07-25

申请号：US18535339

申请日：2023-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonghyun BAEK ,  Hyungu KANG ,  Cheol-Woo LEE ,  Sunghwan YOON ,  Eunjeong IM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/5381 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A semiconductor package including first and second chip stacks each including semiconductor chips having an offset stack structure, the second chip stack horizontally spaced apart from the first chip stack, a first buffer chip on the substrate and at a side of the first chip stack, a second buffer chip on the substrate and at a side of the second chip stack, a connection substrate on the first and second chip stacks, a first mold layer covering the substrate, the first chip stack, and the second stack and exposing a top surface of the connection substrate, third and fourth chip stacks each including semiconductor chips having an offset stack structure on the first mold layer and, the fourth chip stack horizontally spaced apart from the third chip stack, and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack may be provided.