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公开(公告)号:US20240153856A1
公开(公告)日:2024-05-09
申请号:US18386003
申请日:2023-11-01
发明人: Joonghyun BAEK , Hyunsoo CHUNG , Dongok KWAK , Eunjeong IM
IPC分类号: H01L23/498 , H01L23/00 , H01L23/31 , H01L25/10 , H10B80/00
CPC分类号: H01L23/49822 , H01L23/3107 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L24/73 , H01L25/105 , H10B80/00 , H01L24/32 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438 , H01L2924/1441 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311
摘要: A semiconductor package having a lower redistribution structure includes a redistribution insulation layer, a plurality of ball pads in the redistribution insulation layer apart from one another, a double via which includes a first active via and a dummy via located on at least one of the plurality of ball pads and apart from each other in the redistribution insulation layer, and a first active redistribution layer electrically connected to the first active via in the redistribution insulation layer, solder balls electrically connected to the plurality of ball pads under the lower redistribution structure, a first semiconductor chip on the lower redistribution structure and electrically connected to the first active via and the first active redistribution layer of the lower redistribution structure, and a molding layer molding the first semiconductor chip on the lower redistribution structure.
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公开(公告)号:US20240079380A1
公开(公告)日:2024-03-07
申请号:US18334062
申请日:2023-06-13
发明人: Joonghyun BAEK , Jaekyu SUNG , Dongok KWAK , Taeyoung LEE
IPC分类号: H01L25/065 , H01L23/00
CPC分类号: H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L2224/32145 , H01L2224/48147 , H01L2224/48227 , H01L2224/73215 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
摘要: A stacked semiconductor package may include a package base substrate, a first chip stack including a first semiconductor chips stacked sequentially on the package base substrate, a second chip stack including second semiconductor chips stacked sequentially on the first chip stack, and bonding wires electrically connecting the first semiconductor chips and the second semiconductor chips to the package base substrate. Each of the first semiconductor chips may be shifted by a first interval in a first horizontal direction to have a step shape. Each of the second semiconductor chips may be shifted by the first interval in a second horizontal direction, opposite to the first horizontal direction, to have a step shape. A lowermost second semiconductor chip may be shifted from an uppermost first semiconductor chip by a second interval in the second direction. The second interval may be greater than the first interval.
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公开(公告)号:US20210305117A1
公开(公告)日:2021-09-30
申请号:US17060805
申请日:2020-10-01
发明人: Suchang LEE , Dongok KWAK
IPC分类号: H01L23/36 , H01L23/538
摘要: A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more.
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公开(公告)号:US20140117528A1
公开(公告)日:2014-05-01
申请号:US14066008
申请日:2013-10-29
发明人: Jaebum BYUN , Heeyoub KANG , Dongok KWAK , Junghoon KIM , Joonyoung OH , Won-Hwa LEE , Jae-Woo JEONG , Jinyoung CHOI
IPC分类号: H01L23/367
CPC分类号: H01L23/3675 , H01L23/367 , H01L23/38 , H01L23/42 , H01L23/552 , H01L24/06 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/0401 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2224/73253
摘要: A semiconductor module may include a heat-transferring part connecting at least one of a control device, a buffer semiconductor device, and a memory device to a connector. The heat-transferring part may be configured to have a thermal conductivity higher than the substrate. Accordingly, during the operation of the semiconductor module, the connector can have a temperature lower than the devices.
摘要翻译: 半导体模块可以包括将控制装置,缓冲半导体装置和存储装置中的至少一个连接到连接器的传热部。 传热部件可以被配置为具有比基板高的导热性。 因此,在半导体模块的操作期间,连接器可以具有比器件低的温度。
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