公开(公告)号：US20240145306A1

公开(公告)日：2024-05-02

申请号：US18236165

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyosoo CHOO ,  Daeseok Byeon ,  Taehong Kwon

IPC: H01L21/78 ,  H01L23/00 ,  H10B43/27

CPC classification number: H01L21/78 ,  H01L24/80 ,  H01L24/94 ,  H10B43/27 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.

公开(公告)号：US20250095745A1

公开(公告)日：2025-03-20

申请号：US18677536

申请日：2024-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-Hong KWON ,  Gyosoo CHOO ,  Myung Uk PARK ,  Donggeun LEE

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16

Abstract: A flash memory includes a memory block connected to word lines, an address decoder that selects one or more of the word lines, a first pass transistor connected to the address decoder, a second pass transistor connected in series with the first pass transistor and connected to one word line among the word lines, a first driver circuit that controls a gate voltage of the first pass transistor based on a first enable signal, and a second driver circuit that controls a gate voltage of the second pass transistor based on a second enable signal. Based on the memory block being an unselected memory block during an erase operation, the first driver circuit controls the first pass transistor to be in a floating state, the second driver circuit controls a power voltage to be provided to a gate of the second pass transistor.

公开(公告)号：US20240194265A1

公开(公告)日：2024-06-13

申请号：US18386472

申请日：2023-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyosoo CHOO ,  Daeseok BYEON

IPC: G11C16/08 ,  G11C5/06 ,  G11C16/04 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/08 ,  G11C5/063 ,  G11C16/0483 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Memory devices having an asymmetric page buffer array architecture are provided. The memory device includes a memory cell array in which each of plural memory planes is included in a cell array structure, and a row decoder array and a page buffer array included in a peripheral circuit structure vertically overlap the cell array structure. The row decoder array is buried in a region vertically overlapping a word line step region of the cell array structure and a partial region of a memory cell array adjacent to the word line step region. In the page buffer array, bit lines of a partial region of the memory cell array in which the row decoder array is buried are connected to a first page buffer array, and bit lines not included in the partial region are connected to a second page buffer array.

公开(公告)号：US20240153830A1

公开(公告)日：2024-05-09

申请号：US18139707

申请日：2023-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyosoo CHOO ,  Daeseok BYEON ,  Sunghun KIM

IPC: H01L21/66 ,  G01R31/26 ,  H10B80/00

CPC classification number: H01L22/34 ,  G01R31/2607 ,  H10B80/00

Abstract: A semiconductor device includes a semiconductor die, a detection structure, a path control circuit and a detection circuit. The semiconductor die includes a central region in which a semiconductor integrated circuit is provided and an external region surrounding the central region. The detection structure is provided in the external region. The path control circuit includes a plurality of switches that controls electrical connection of the detection structure. The detection circuit determines whether a defect is present in the semiconductor die and a location of the defect based on a difference signal. The difference signal corresponds to a difference between a forward direction test output signal and a backward direction test output signal obtained by propagating a test input signal through the detection structure in a forward direction and a backward direction, respectively, via the path control circuit.