公开(公告)号：US20240222451A1

公开(公告)日：2024-07-04

申请号：US18243818

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wandon Kim ,  Jaeseoung Park ,  Hyunwoo Kim ,  Hyunbae Lee ,  Jeonghyuk Yim ,  Hyoseok Choi

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region extending in a first direction, a gate structure extending in a second direction, a source/drain region on the active region, a first contact structure connected to the source/drain region, and a second contact structure connected to the first contact structure. The second contact structure includes a first layer including a first grain and a second layer including second grains on the first layer. Within the first layer, a maximum vertical distance between a lowermost end of the first grain and an uppermost end of the first grain is equal to a vertical distance between a lowermost end of the first layer and an uppermost end of the first layer. A size of the first grain is greater than a size of each of the second grains. A width of the first layer is greater than a width of the first contact structure.

公开(公告)号：US20220230956A1

公开(公告)日：2022-07-21

申请号：US17535818

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Euibok Lee ,  Wandon Kim ,  Minjoo Lee ,  Hyunbae Lee

IPC: H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.

公开(公告)号：US11929366B2

公开(公告)日：2024-03-12

申请号：US17846177

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0673

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US12230682B2

公开(公告)日：2025-02-18

申请号：US17672033

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoontae Hwang ,  Geunwoo Kim ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L29/417 ,  H01L23/522 ,  H01L29/45

Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

公开(公告)号：US11830874B2

公开(公告)日：2023-11-28

申请号：US17578982

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Yoon Tae Hwang ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/088 ,  H01L23/528 ,  H01L23/5226 ,  H01L29/4941

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.

公开(公告)号：US11374001B2

公开(公告)日：2022-06-28

申请号：US16851476

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung Noh ,  Wandon Kim ,  Hyunbae Lee ,  Donggon Yoo ,  Dong-Chan Lim

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/535

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US11233050B2

公开(公告)日：2022-01-25

申请号：US16860279

申请日：2020-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwoo Kim ,  Yoon Tae Hwang ,  Wandon Kim ,  Hyunbae Lee

IPC: H01L27/088 ,  H01L29/49 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern and extending in a first direction; a source/drain pattern on the active pattern and adjacent to a side of the gate electrode; and an active contact in a contact hole on the source/drain pattern, wherein the active contact includes a first contact in a lower region of the contact hole, the first contact including a barrier pattern and a conductive pattern; a diffusion barrier layer on the first contact; and a second contact on the diffusion barrier layer, and a top surface of the diffusion barrier layer is coplanar with a top surface of the barrier pattern of the first contact.