公开(公告)号：US20230411294A1

公开(公告)日：2023-12-21

申请号：US18457000

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Saehan PARK ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

公开(公告)号：US20230086084A1

公开(公告)日：2023-03-23

申请号：US17554483

申请日：2021-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Inchan Hwang ,  Gunho Jo ,  Jeonghyuk Yim ,  Byounghak Hong ,  Kang-ill Seo ,  Ming He ,  JaeHyun Park ,  Mehdi Saremi ,  Rebecca Park ,  Harsono Simka ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L21/8234

Abstract: Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

公开(公告)号：US20220230924A1

公开(公告)日：2022-07-21

申请号：US17223803

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk Yim ,  Kang III Seo

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/66

Abstract: Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1st fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2nd fin structures on the substrate, wherein a fin pitch of the 2nd fin structures is smaller than a fin pitch of the 1st fin structures.

公开(公告)号：US20250063804A1

公开(公告)日：2025-02-20

申请号：US18668920

申请日：2024-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Suyoung BAE ,  Ohseong Kwon ,  Jaeyeol Song ,  Jeonghyuk Yim

IPC: H01L21/8238 ,  H01L21/308 ,  H01L27/092

Abstract: Provided is a semiconductor device and method of manufacturing same, the method including: preparing a substrate including first and second regions; forming a first and second channel patterns in the first and second regions, wherein the first and second channel patterns each include a plurality of semiconductor patterns vertically stacked on the substrate, an inner region, and an outer region; forming a high-k dielectric layer covering the first channel pattern and the second channel pattern; forming a first protective mask on the high-k dielectric layer in the first region and the second region; removing the first protective mask from the first outer region and the second outer region; and forming an additional mask layer surrounding the first channel pattern and the second channel pattern, wherein the additional mask layer does not have etch selectivity with the first protective mask.

公开(公告)号：US11923365B2

公开(公告)日：2024-03-05

申请号：US17387178

申请日：2021-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk Yim ,  Ki-Il Kim ,  Gil Hwan Son ,  Kang Ill Seo

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823871 ,  H01L29/0665 ,  H01L29/401 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78645

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

公开(公告)号：US11094586B2

公开(公告)日：2021-08-17

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon Choi ,  Jaeung Koo ,  Kwansung Kim ,  Bo Yun Kim ,  Wandon Kim ,  Boun Yoon ,  Jeonghyuk Yim ,  Yeryung Jeon

IPC: H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L21/3105

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US10950709B2

公开(公告)日：2021-03-16

申请号：US16458412

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk Yim ,  Wandon Kim ,  Weonhong Kim ,  Jongho Park ,  Hyeonjun Baek ,  Byounghoon Lee ,  Sangjin Hyun

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including first and second active regions, first and second active patterns disposed on the first and second active regions, respectively, first and second gate electrodes crossing the first and second active patterns, respectively, a first gate insulating pattern interposed between the first active pattern and the first gate electrode, and a second gate insulating pattern interposed between the second active pattern and the second gate electrode. The first gate insulating pattern includes a first dielectric pattern and a first ferroelectric pattern disposed on the first dielectric pattern. The second gate insulating pattern includes a second dielectric pattern. A threshold voltage of a transistor in the first active region is different from a threshold voltage of a transistor in the second active region.

公开(公告)号：US10784260B2

公开(公告)日：2020-09-22

申请号：US16116295

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho Park ,  Wandon Kim ,  Jeonghyuk Yim ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.

公开(公告)号：US12262560B2

公开(公告)日：2025-03-25

申请号：US18425476

申请日：2024-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonghyuk Yim ,  Ki-Il Kim ,  Gil Hwan Son ,  Kang Ill Seo

IPC: H10D84/85 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03

Abstract: Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

公开(公告)号：US11769728B2

公开(公告)日：2023-09-26

申请号：US17159972

申请日：2021-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saehan Park ,  Hoonseok Seo ,  Jeonghyuk Yim ,  Ki-il Kim ,  Gil Hwan Son

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/822 ,  H01L23/48 ,  H01L23/00 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0694 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05176

Abstract: Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.