公开(公告)号：US11936384B2

公开(公告)日：2024-03-19

申请号：US18092507

申请日：2023-01-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyun Choi ,  Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/037 ,  G01R31/3185 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  G01R31/318541 ,  H03K3/037 ,  H03K3/35625

Abstract: A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.

公开(公告)号：US11528018B2

公开(公告)日：2022-12-13

申请号：US16930658

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwoo Kim ,  Minsu Kim ,  Yonggeol Kim ,  Hyun Lee ,  Hyunchul Hwang

IPC: H03K3/3562 ,  H03K3/037 ,  H03K19/00

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

公开(公告)号：US10348299B2

公开(公告)日：2019-07-09

申请号：US16001701

申请日：2018-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/00 ,  G06F1/3237

Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

公开(公告)号：US12015408B2

公开(公告)日：2024-06-18

申请号：US17712465

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/012 ,  H03K3/013 ,  H03K3/356

CPC classification number: H03K3/356191 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356121

Abstract: A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

公开(公告)号：US11658656B2

公开(公告)日：2023-05-23

申请号：US17515607

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Youngo Lee

IPC: H03K17/687 ,  H03K3/356

CPC classification number: H03K17/6871 ,  H03K3/356

Abstract: A clock gating cell including: a first circuit configured to receive an enable signal and an inverted output clock signal and generate a first signal through a first node; a second circuit configured to receive the first signal and generate an inverted first signal; a third circuit configured to receive the first signal, the inverted first signal, and an input clock signal, generate the first signal by being connected to the first circuit through the first node, and generate the inverted output clock signal through a second node; and a fourth circuit configured to receive the first signal, generate the inverted output clock signal by being connected to the third circuit through the second node, and generate the output clock signal, wherein the third circuit includes a pair of transistors receiving the input clock signal.

公开(公告)号：US10320369B2

公开(公告)日：2019-06-11

申请号：US15903507

申请日：2018-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/20 ,  G11C19/28 ,  G11C27/02 ,  H03K3/356 ,  G11C11/4074 ,  G11C11/4076

Abstract: In a sequential circuit, a first stage is configured to charge a voltage of a first node in response to a clock, and to discharge the voltage of the first node in response to the clock, a voltage of a second node, and data; a second stage is configured to charge the voltage of the second node in response to the clock, and to discharge the voltage of the second node in response to the clock and a logic signal; a combinational logic is configured to generate the logic signal based on the voltage of the first node, the voltage of the second node, and the data; and a latch circuit is configured to latch the voltage of the second node in response to the clock.

公开(公告)号：US10014862B2

公开(公告)日：2018-07-03

申请号：US15660527

申请日：2017-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013 ,  Y02D10/128

Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

公开(公告)号：US09762240B2

公开(公告)日：2017-09-12

申请号：US15153799

申请日：2016-05-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/00

CPC classification number: H03K19/0016 ,  G06F1/3237 ,  H03K19/0013

Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.

公开(公告)号：US11784647B2

公开(公告)日：2023-10-10

申请号：US17503791

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim ,  Janghwan Yoon

IPC: H03K19/096 ,  H03K19/20

CPC classification number: H03K19/0963 ,  H03K19/20

Abstract: An integrated circuit includes a first circuit, a second circuit, and an inverter. The first circuit receives a first input signal, an inverted clock signal, a first logic level of a first output node, and a logic level of a second output node to determine a second logic level of a first output node. The second circuit receives the first input signal, the clock signal, the first logic level, and the second logic level to determine a logic level of the second output node. The inverter receives a second input signal to output the inverted second input signal to the first circuit or the second circuit. A logic level of the first output node or a logic level of the second output node is output as an output signal when a logic level of the clock signal is a first logic level.

公开(公告)号：US20210270899A1

公开(公告)日：2021-09-02

申请号：US17025511

申请日：2020-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonhyun Choi ,  Hyunchul Hwang ,  Minsu Kim

IPC: G01R31/3185 ,  G06F1/10 ,  G01R31/3177

Abstract: High-speed flipflop circuits are disclosed. The flipflop circuit may latch a data input signal or a scan input signal using a first signal, a second signal, a third signal, and a fourth signal generated inside the flipflop circuit, and may output an output signal and an inverted output signal. The flipflop circuit includes a first signal generation circuit configured to generate the first signal; a second signal generation circuit configured to generate the second signal; a third signal generation circuit configured to receive the second signal and generate the third signal; and an output circuit configured to receive the clock signal and the second signal, and output an output signal and an inverted output signal.