中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

14 records (took 0.015 seconds)

    Programming method of a nonvolatile memory device and a method thereof
    3.
    发明授权
    Programming method of a nonvolatile memory device and a method thereof 有权

    公开(公告)号：US10157674B2

    公开(公告)日：2018-12-18

    申请号：US15714155

    申请日：2017-09-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Doo-hyun Kim ,  Il-han Park ,  Jong-hoon Lee

    IPC: G11C16/04 ,  G11C16/14 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34

    Abstract: A soft erase method of a memory device including applying a program voltage to a first memory cell in at least one of program loops when a plurality of program loops are performed to program the first memory cell into a Nth programming state, wherein the first memory cell is included in a selected memory cell string connected to a selected first bit line and is connected to a selected word line; and soft erasing a second memory cell by applying, in a first verification interval, a read voltage for verifying a programming state of the first memory cell to the selected word line and applying a first prepulse to a gate of a string select transistor of each of a plurality of unselected memory cell strings connected to the first bin line and a plurality of unselected memory cell strings connected to an unselected second bit line.

    Non-volatile memory device and erasing method of the same
    5.
    发明授权
    Non-volatile memory device and erasing method of the same 有权

    公开(公告)号：US11081186B2

    公开(公告)日：2021-08-03

    申请号：US17019889

    申请日：2020-09-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Young Lee ,  Young-sik Rho ,  Il-han Park

    IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Provided are a non-volatile memory device and an erasing method thereof. The non-volatile memory device including a memory cell region includes first metal pads and a memory block, the memory block being disposed in a memory cell region and includes a plurality of cell strings having a plurality of memory cells stacked in a direction perpendicular to a substrate between a plurality of bit line and a common source line of the memory block, and a peripheral circuit region including second metal pads and a control logic, and vertically connected to the memory cell region by the first metal pads and the second metal pads, wherein the control logic configured to, perform control such that a first erase voltage is provided to the plurality of bit lines and the common source line, and a first erase control voltage is provided to a plurality of first selection lines and a second selection line during a first erase period, the plurality of first selection lines being used for selecting a corresponding cell string from among the plurality of cell strings and the second selection line being disposed closest to the common source line, and perform control such that a second erase voltage is provided to the plurality of bit lines, and such that a second erase control voltage is provided to at least one first selection line among the plurality of first selection lines during a second erase period, the second erase control voltage being lower than the first erase control voltage.

    Non-volatile memory device and erasing method of the same
    6.
    发明授权
    Non-volatile memory device and erasing method of the same 有权

    公开(公告)号：US10777278B2

    公开(公告)日：2020-09-15

    申请号：US16401877

    申请日：2019-05-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-Young Lee ,  Young-sik Rho ,  Il-han Park

    IPC: G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/34

    Abstract: Provided are a non-volatile memory device and an erasing method thereof. The erasing method of the non-volatile memory device including a plurality of cell strings in which memory cells and selection transistors are connected, includes: performing a first erase operation based on an erase voltage provided to a first electrode of at least one of the selection transistors and an erase control voltage provided to a second electrode of the at least one of the selection transistors; determining whether there are slow erase cells by performing a multiple erase verify operation based on first and second verify voltages, the second verify voltage being higher than the first verify voltage; adjusting, when there are slow erase cells, the erase control voltage such that a voltage difference between the erase voltage and the erase control voltage increases; and performing a second erase operation based on the adjusted erase control voltage.

    Nonvolatile memory device and operating method thereof
    8.
    发明授权
    Nonvolatile memory device and operating method thereof 有权

    公开(公告)号：US10553291B2

    公开(公告)日：2020-02-04

    申请号：US16015959

    申请日：2018-06-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-yun Lee ,  Il-han Park ,  Jun-yong Park ,  Byung-soo Kim

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  H01L27/11582

    Abstract: Provided is a nonvolatile memory device and an operating method thereof. The operating method for programming a first memory block from among a plurality of memory blocks includes: programming a first word line connected to the first memory block by sequentially executing first to Nth (N is a natural number) programming loops; applying a voltage generated by regulating a first pump voltage of a first charge pump to the first word line as a dummy verifying voltage after the programming is completed; generating a first detection count based on the first pump voltage and a first reference voltage; and outputting a bad block setting signal for setting the first memory block as a bad block based on a result of comparing the first detection count with the first reference count.

    Nonvolatile memory device having a vertical structure and a memory system including the same
    9.
    发明授权
    Nonvolatile memory device having a vertical structure and a memory system including the same 有权

    公开(公告)号：US11211403B2

    公开(公告)日：2021-12-28

    申请号：US17073653

    申请日：2020-10-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bong-soon Lim ,  Jin-young Kim ,  Sang-won Shim ,  Il-han Park

    IPC: G11C11/34 ,  H01L27/11582 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/535 ,  H01L27/1157 ,  H01L23/522 ,  H01L27/11565 ,  G11C16/08 ,  H01L27/11575 ,  G11C16/04

    Abstract: A nonvolatile memory device including: a first semiconductor layer comprising a plurality of first word lines extending in a first direction, a first upper substrate and a first memory cell array, a second semiconductor layer including a plurality of second word lines extending in the first direction, second and third upper substrates adjacent to each other in the first direction and a second memory cell array, wherein the second memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, wherein the first semiconductor layer and the second semiconductor layer share a plurality of bit lines extending in a second direction, and a third semiconductor layer under the second semiconductor layer in a third direction perpendicular to the first and second directions, wherein the third semiconductor layer includes a lower substrate that includes a plurality of row decoder circuits and a plurality of page buffer circuits, wherein the first vertical structure includes a first via area in which a first through-hole via is provided, wherein the first through-hole via passes through the first vertical structure and connects a first bit line and a first page buffer circuit, and the second vertical structure includes a first partial block, wherein the first partial block overlaps the first via area in the first direction.

Patent Agency Ranking