公开(公告)号：US20220223619A1

公开(公告)日：2022-07-14

申请号：US17706426

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  DONG-SIK LEE ,  SUNG-MIN HWANG ,  JOON-SUNG LIM

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

公开(公告)号：US20190035798A1

公开(公告)日：2019-01-31

申请号：US15954151

申请日：2018-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  DONG-SIK LEE ,  JOON-SUNG LIM

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/06 ,  H01L23/532

CPC classification number: H01L27/11286 ,  H01L23/53295 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/0649

Abstract: A three-dimensional semiconductor memory device includes a substrate including a peripheral circuit region and a cell array region, a plurality of peripheral gate stacks disposed in the peripheral circuit region, and an electrode structure disposed in the cell array region. The electrode structure includes a lower electrode, a lower insulating layer disposed on the lower electrode, and upper electrodes and upper insulating layers alternately stacked on the lower insulating layer. The lower insulating layer extends from the cell array region into the peripheral circuit region and covers the peripheral gate stacks. The lower insulating layer includes a first lower insulating layer and a second lower insulating layer sequentially stacked on one another. The first lower insulating layer includes a first insulating material, and the second lower insulating layer includes a second insulating material different from the first insulating material.

公开(公告)号：US20240015970A1

公开(公告)日：2024-01-11

申请号：US18372885

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  HOJUN SEONG ,  JOONHEE LEE ,  JOON-SUNG LIM ,  EUNTAEK JUNG

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US20220102306A1

公开(公告)日：2022-03-31

申请号：US17240641

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HO AHN ,  JI WON KIM ,  SUNG-MIN HWANG ,  JOON-SUNG LIM ,  SUK KANG SUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

公开(公告)号：US20210225870A1

公开(公告)日：2021-07-22

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  HOJUN SEONG ,  JOONHEE LEE ,  JOON-SUNG LIM ,  EUNTAEK JUNG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11539

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.