公开(公告)号：US09165354B2

公开(公告)日：2015-10-20

申请号：US13908608

申请日：2013-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Kyu Son ,  Hyo-Cheon Kang ,  Deok-Yong Kim ,  Jae-Kwan Park ,  Jeong-Ho Ahn ,  Soo-Bok Chin

IPC: G06K9/00 ,  G06T7/00 ,  G06T7/40

CPC classification number: G06T7/0004 ,  G06T7/0006 ,  G06T7/42 ,  G06T2207/10061 ,  G06T2207/20056 ,  G06T2207/30148

Abstract: Methods of analyzing photolithography processes are provided. The methods may include obtaining an image from a pattern formed on a wafer and obtaining dimensions of the image. The methods may further include converting the dimensions into a profile graph and then dividing the profile graph into a low-frequency band profile graph and a high-frequency band profile graph.

Abstract translation: 提供了分析光刻工艺的方法。 所述方法可以包括从形成在晶片上的图案获得图像并获得图像的尺寸。 所述方法还可以包括将维度转换成简档图，然后将简档图划​​分成低频带轮廓图和高频带轮廓图。

公开(公告)号：US20140037186A1

公开(公告)日：2014-02-06

申请号：US13908608

申请日：2013-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woong-Kyu Son ,  Hyo-Cheon Kang ,  Deok-Yong Kim ,  Jae-Kwan Park ,  Jeong-Ho Ahn ,  Soo-Bok Chin

IPC: G06T7/00

CPC classification number: G06T7/0004 ,  G06T7/0006 ,  G06T7/42 ,  G06T2207/10061 ,  G06T2207/20056 ,  G06T2207/30148

Abstract: Methods of analyzing photolithography processes are provided. The methods may include obtaining an image from a pattern formed on a wafer and obtaining dimensions of the image. The methods may further include converting the dimensions into a profile graph and then dividing the profile graph into a low-frequency band profile graph and a high-frequency band profile graph.

Abstract translation: 提供了分析光刻工艺的方法。 所述方法可以包括从形成在晶片上的图案获得图像并获得图像的尺寸。 所述方法还可以包括将维度转换成简档图，然后将简档图划​​分成低频带轮廓图和高频带轮廓图。

公开(公告)号：US09093454B2

公开(公告)日：2015-07-28

申请号：US14186617

申请日：2014-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yong Park ,  Jae-Hwang Sim ,  Young-Ho Lee ,  Kyung-Lyul Moon ,  Jae-Kwan Park

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/115

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823456 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of forming a semiconductor device, a feature layer is provided on a substrate and a mask layer is provided on the feature layer. A portion of the mask layer is removed in a first region of the semiconductor device where fine features of the feature layer are to be located, the mask layer remaining in a second region of the semiconductor device where broad features of the feature layer are to be located. A mold mask pattern is provided on the feature layer in the first region and on the mask layer in the second region. A spacer layer is provided on the mold mask pattern in the first region and in the second region. An etching process is performed to etch the spacer layer so that spacers remain at sidewalls of pattern features of the mold mask pattern, and to etch the mask layer in the second region to provide mask layer patterns in the second region. The feature layer is etched using the mask layer patterns as an etch mask in the second region and using the spacers as an etch mask in the first region to provide a feature layer pattern having fine features in the first region and broad features in the second region.

Abstract translation: 在形成半导体器件的方法中，在衬底上提供特征层，并且在特征层上设置掩模层。 掩模层的一部分在半导体器件的第一区域被去除，其中特征层的精细特征将被定位，掩模层保留在半导体器件的第二区域中，其中特征层的广泛特征将是 位于。 模具掩模图案设置在第一区域中的特征层和第二区域中的掩模层上。 间隔层设置在第一区域和第二区域中的模具掩模图案上。 执行蚀刻工艺以蚀刻间隔层，使得间隔物保留在模具掩模图案的图案特征的侧壁处，并且蚀刻第二区域中的掩模层以在第二区域中提供掩模层图案。 使用掩模层图案作为第二区域中的蚀刻掩模蚀刻特征层，并且在第一区域中使用间隔物作为蚀刻掩模来提供在第一区域中具有精细特征的特征层图案，并且在第二区域中具有广泛特征 。