公开(公告)号：US20170116954A1

公开(公告)日：2017-04-27

申请号：US15271837

申请日：2016-09-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hoon BAEK ,  Hyunwook LIM ,  Kwi Sung YOO ,  Eun-Young JIN ,  Kyongho KIM ,  JaeYoul LEE ,  Youngmin CHOI

IPC: G09G5/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/08 ,  H03L7/099

CPC classification number: G09G5/008 ,  G09G3/2096 ,  G09G2310/027 ,  G09G2330/10 ,  G09G2370/10 ,  G09G2370/16 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/095

Abstract: A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

公开(公告)号：US20190385508A1

公开(公告)日：2019-12-19

申请号：US16257420

申请日：2019-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun CHUNG ,  HONGKI KWON ,  TaeWoo KIM ,  Jinyong PARK ,  JaeYoul LEE

IPC: G09G3/20 ,  H04N19/176 ,  H04N19/182

Abstract: The present invention provides a display driver circuit. A determination circuit is configured to select a first mode for encoding first image data based on a first set of conditions respectively corresponding to a first set of modes. An encoder is configured to encode the first image data in the first mode. The determination circuit is additionally configured to select a second mode for encoding second image data received (n−1)th after the first image data are received; and to select a third mode for encoding third image data received (n)th after the first image data are received, based on a second set of conditions respectively corresponding to the first set of modes. A second condition in the second set of the conditions corresponding to the second mode includes a wider range of values than a first condition in the first set of the conditions corresponding to the second mode.

公开(公告)号：US20180083641A1

公开(公告)日：2018-03-22

申请号：US15650263

申请日：2017-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho RYU ,  Dongmyung LEE ,  JaeYoul LEE ,  Kilhoon LEE ,  Jung-Pil LIM

IPC: H03L7/081 ,  H03L7/087 ,  H03L7/07 ,  H03K5/05 ,  H03K5/24 ,  G06F1/10

CPC classification number: H03L7/0814 ,  G06F1/10 ,  H03K5/05 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/087

Abstract: A delay locked loop includes a first delay line and a second delay line. The first delay line is configured to generate a first delay clock, signal by passing an input clock, signal through a first number of logic gates among a plurality of logic gates and a second delay clock signal by passing the input clock signal through a second number of logic gates among the plurality of logic gates. The second delay line is configured to output an output clock signal based on one of a first signal having a first phase of the first delay clock signal, a second signal having a second phase of the second delay clock signal, and an interpolation signal having a third phase adjusted in stages by a reference value between the first phase and the second phase.

公开(公告)号：US20200265770A1

公开(公告)日：2020-08-20

申请号：US16866930

申请日：2020-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hojun CHUNG ,  HONGKI KWON ,  TaeWoo KIM ,  Jinyong PARK ,  JaeYoul LEE

IPC: G09G3/20 ,  H04N19/182 ,  H04N19/176

Abstract: The present invention provides a display driver circuit. A determination circuit is configured to select a first mode for encoding first image data based on a first set of conditions respectively corresponding to a first set of modes. An encoder is configured to encode the first image data in the first mode. The determination circuit is additionally configured to select a second mode for encoding second image data received (n−1)th after the first image data are received; and to select a third mode for encoding third image data received(n)th after the first image data are received, based on a second set of conditions respectively corresponding to the first set of modes. A second condition in the second set of the conditions corresponding to the second mode includes a wider range of values than a first condition in the first set of the conditions corresponding to the second mode.

公开(公告)号：US20190156728A1

公开(公告)日：2019-05-23

申请号：US16004926

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Hoon YU ,  Taehyun KIM ,  Byoungyoon JANG ,  JaeYoul LEE

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3611 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2320/029 ,  G09G2320/103 ,  G09G2330/028 ,  G09G2340/16 ,  G09G2370/08

Abstract: A display device is provided. The display device may include pixels arranged in rows and columns, gate drivers connected to the rows of the pixels through gate lines, source drivers connected to the columns of the pixels through source lines, and a timing controller configured to control the gate drivers and the source drivers. The source driver associated with the specific pixel among the source drives may first supply an overdrive voltage corresponding to a final overdrive value to a source line connected to the specific pixel and then supply a source line voltage corresponding to a current value of the specific pixel to the source line. The overdrive controller may change weight values of at least two overdrive values based on a position of the specific pixel and interpolate the at least two overdrive values.

公开(公告)号：US20170097649A1

公开(公告)日：2017-04-06

申请号：US14874758

申请日：2015-10-05

Applicant: Samsung Electronics Co., Ltd. ,  Korea University Research and Business Foundation

Inventor： JaeYoul LEE ,  Jeongpyo KIM ,  Yong Sin KIM ,  Seong Jin YUN

IPC: G05F1/575 ,  G09G3/36

CPC classification number: G05F1/575 ,  G09G3/3696 ,  G09G2330/021

Abstract: A low drop-out (LDO) regulator includes a pass transistor, a feedback circuit, an error amplifier, and a compensation unit. The pass transistor is configured to regulate a power supply and output an output voltage according to a control signal. The feedback circuit is configured to generate a feedback voltage based on the output voltage. The error amplifier is configured to output a comparison signal in response to a reference voltage and the feedback voltage. The compensation circuit is configured to generate a negative capacitance in association with a first node connected to a gate electrode of the pass transistor.