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    METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR
    3.
    发明公开
    METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR 审中-公开

    公开(公告)号：US20240103809A1

    公开(公告)日：2024-03-28

    申请号：US18139567

    申请日：2023-04-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Jin CHANG ,  Soon-Wan KWON ,  Seok Ju YUN ,  Jaehyuk LEE ,  Sungmeen MYUNG ,  Daekun YOON

    IPC: G06F7/507 ,  G06F7/504 ,  G06F7/544

    CPC classification number: G06F7/507 ,  G06F7/504 ,  G06F7/5443

    Abstract: Provided is a computation method of a memory processor configured to perform an operation between a first vector including first elements and a second vector including second elements, the first elements including respective first bits and the second elements including respective second bits, the method performed by the memory processor including: applying, to single-bit operation gates, the respective first bits and the respective second bits; obtaining bit operation result sum values for the respective first and second elements based on bit operation results obtained using the single-bit operation gates; and obtaining an operation result of the first vector and the second vector based on the bit operation result sum value.

    MEMORY AND METHOD WITH IN-MEMORY COMPUTING DEFECT DETECTION
    7.
    发明公开
    MEMORY AND METHOD WITH IN-MEMORY COMPUTING DEFECT DETECTION 审中-公开

    公开(公告)号：US20240071548A1

    公开(公告)日：2024-02-29

    申请号：US18091258

    申请日：2022-12-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungmeen MYUNG ,  Seok Ju YUN ,  Jaehyuk LEE ,  Seungchul JUNG

    IPC: G11C29/36 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C29/36 ,  G11C29/44 ,  G11C29/785 ,  G11C2029/3602

    Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.

    COMPUTING DEVICE AND METHOD USING MULTIPLIER-ACCUMULATOR
    8.
    发明申请
    COMPUTING DEVICE AND METHOD USING MULTIPLIER-ACCUMULATOR 有权

    公开(公告)号：US20230075348A1

    公开(公告)日：2023-03-09

    申请号：US17735492

    申请日：2022-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyuk LEE ,  Sang Joon KIM ,  Seungchul JUNG ,  Sungmeen MYUNG

    IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03K19/21 ,  G06N3/04

    Abstract: A multiplier-accumulator includes: a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines and to output partial product results between the input bit sequence and the weight bit sequence; an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is converted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence; and an outputter configured to generate an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed.

    METHOD FOR PROCESSING DATA AND ELECTRONIC DEVICE FOR SUPPORTING SAME
    9.
    发明申请
    METHOD FOR PROCESSING DATA AND ELECTRONIC DEVICE FOR SUPPORTING SAME 审中-公开

    公开(公告)号：US20200379550A1

    公开(公告)日：2020-12-03

    申请号：US16891225

    申请日：2020-06-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junwhon UHM ,  Nari KIM ,  Mincheol SEO ,  Jaehyuk LEE ,  Sungchul PARK ,  Jiyoon PARK ,  Yongsang YUN

    IPC: G06F3/01 ,  G02B27/01 ,  G06T7/70 ,  G06F1/3212

    Abstract: An electronic device according to certain embodiments may include a communication circuitry; a camera; a display; a sensor; and at least one processor operably connected to the communication circuitry, the camera, the display, and the sensor, wherein the at least one processor is configured to: acquire an image through the camera; acquire, through the sensor, information on a position and a orientation of the electronic device; select, from among the electronic device and an external electronic device, a selected electronic device to produce a virtual image related to the image; when the selected electronic device is the external electronic device transmit, through the communication circuitry, the information on the position and the orientation of the electronic device and the image to the external electronic device; receive, through the communication circuitry, the virtual image; and display the virtual image through the display.

    METHOD AND MEMORY DEVICE WITH IN-MEMORY COMPUTING
    10.
    发明公开
    METHOD AND MEMORY DEVICE WITH IN-MEMORY COMPUTING 审中-公开

    公开(公告)号：US20240241694A1

    公开(公告)日：2024-07-18

    申请号：US18355046

    申请日：2023-07-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daekun YOON ,  Soon-Wan KWON ,  Seok Ju YUN ,  Jaehyuk LEE ,  Dong-Jin CHANG

    IPC: G06F7/544 ,  G06F7/501 ,  G11C7/10

    CPC classification number: G06F7/5443 ,  G06F7/501 ,  G11C7/1012

    Abstract: Disclosed is an in-memory computing device and method. The in-memory computing device includes: a memory unit including bit cells configured to store first input data having a reference-bit-count, receive second input data also having the reference-bit-count, and perform a multiplication operation between the first input data and the second input data; and an operation unit including: a first adder tree configured to output intermediate operation results by adding results of performing the multiplication operation output with respect to each of the bit cells; a branch module configured to branch the intermediate operation results according to an operation mode of the in-memory computing device; and a second adder tree configured to output a final operation result based on an output of the branch module.

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