公开(公告)号：US20240363536A1

公开(公告)日：2024-10-31

申请号：US18634187

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung PARK ,  Heonjong SHIN ,  Jaehyun KANG ,  Youngsoo SONG

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including a first active region including first active patterns spaced apart by a first interval, a second active region including second active patterns spaced apart by a second interval, first and second source/drain regions on the first and second active regions, first and second contact structures connected to the first and second source/drain regions, first and second conductive through-structures connected to the first and second contact structures, a power delivery structure in contact with bottom surfaces of the first and second conductive through-structures, a frontside interconnection structure, and a backside interconnection structure. The first conductive through-structure may be connected to the first source/drain region through the first contact structure. The second conductive through-structure may be connected to the second source/drain region through the frontside interconnection structure. The second interval may be different than the first interval.

公开(公告)号：US20250107150A1

公开(公告)日：2025-03-27

申请号：US18650292

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daesik KIM ,  Seonbae KIM ,  Taeyong KWON ,  Changhee KIM ,  Doohyun LEE ,  Jaehyun KANG ,  Jinyoung PARK ,  Hyunho PARK ,  Jimin YU ,  Jinwook LEE ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active region, a gate structure on the substrate, a plurality of channel layers on the active region, spaced apart from each other and surrounded by the gate structure, a source/drain region in a region at which the active region is recessed, on at least one side of the gate structure, and connected to the channel layers, and a contact plug partially recessing the source/drain region from an upper surface of the source/drain region, electrically connected to the source/drain region, and including a metal-semiconductor compound layer along a recessed surface of the source/drain region and a contact conductor layer on the metal-semiconductor compound layer, wherein the metal-semiconductor compound layer has a first thickness on a side surface of the contact conductive layer and a second thickness on a bottom surface of the contact plug, the second thickness being smaller than the first thickness.

公开(公告)号：US20240321980A1

公开(公告)日：2024-09-26

申请号：US18596772

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong SHIN ,  Jaehyun KANG ,  Seonbae KIM ,  Wangseop LIM ,  Seunghyun HWANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: An integrated circuit device includes a substrate having a main surface and fin-type active regions protruding in a vertical direction from the main surface and extending lengthwise in a first horizontal direction, gate lines extending parallel to one another in a second horizontal direction perpendicular to the first horizontal direction and crossing the fin-type active regions, source/drain regions on the fin-type active regions between the gate lines, an inter-gate insulation layer covering the source/drain regions between the gate lines, active contacts on and in contact with the source/drain regions, and a buried insulation block between adjacent ones of the source/drain regions in the second horizontal direction, the buried insulation block penetrating through at least a portion of the inter-gate insulation layer and having a top surface in contact with a first active contact of the active contacts.