公开(公告)号：US20240168091A1

公开(公告)日：2024-05-23

申请号：US18325162

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ikjin JO ,  Jaewoo PARK ,  Jueon KIM ,  Myoungbo KWAK ,  Junghwan CHOI

IPC: G01R31/317 ,  G01R31/319

CPC classification number: G01R31/31727 ,  G01R31/31726 ,  G01R31/31926

Abstract: A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

公开(公告)号：US20230161558A1

公开(公告)日：2023-05-25

申请号：US17986303

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd. ,  UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： JUN-WOO JANG ,  Jaewoo PARK ,  Faaiz ASIM ,  Jongeun LEE

IPC: G06F7/544 ,  G06F7/50 ,  G06F5/01 ,  H03K19/21

CPC classification number: G06F7/5443 ,  G06F7/50 ,  G06F5/01 ,  H03K19/21

Abstract: A processor-implemented artificial neural network quantization scheme implementation method and apparatus are provided. The method includes receiving input data corresponding to a first M-dimensional vector, receiving a weight parameter corresponding to a second M-dimensional vector, encoding the input data into first bit streams, each having “N” layers, with a predetermined quantization scheme, encoding the weight parameter into second bit streams, each having “N” layers, with the quantization scheme, applying corresponding first and second bit streams to a binary neural network operator, for each of possible combinations between layers of the first bit streams and layers of the second bit streams, receiving a dot product result output based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits and accumulating the shifted BNN operation result, from the BNN operator, and quantizing the dot product result using the quantization scheme.

公开(公告)号：US20220256444A1

公开(公告)日：2022-08-11

申请号：US17573017

申请日：2022-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaewoo PARK ,  Kwangsu LEE ,  Jaemoon CHA

IPC: H04W48/16 ,  H04B1/04 ,  H04W72/04 ,  H04W28/02

Abstract: According to various embodiments, an electronic device may comprise: at least one antenna, a plurality of radio frequency (RF) devices configured to perform generation of a transmission RF signal input to the at least one antenna and/or conversion of a reception RF signal output from the at least one antenna, and at least one processor. The at least one processor may be configured to: detect an error in at least one RF device among the plurality of RF devices, identify at least one RF path associated with the at least one RF device with the error and at least one frequency associated with the at least one RF path, adjust a user equipment (UE) capability supported by the electronic device, by modifying and/or deleting an information element associated with the at least one frequency among at least one information element of the UE capability, based on the at least one RF path, and report the adjusted UE capability to a network.

公开(公告)号：US20230208483A1

公开(公告)日：2023-06-29

申请号：US18115250

申请日：2023-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemoon CHA ,  Jimin KOO ,  Jaewoo PARK ,  Seongju LEE ,  Yeonjoo LEE ,  Hyeyong GO ,  Yeongseob LIM ,  Kyujae JANG ,  Sungyoul CHO

IPC: H04B7/06 ,  H04W52/24 ,  H04W52/36 ,  H04B1/3827

CPC classification number: H04B7/0608 ,  H04W52/245 ,  H04W52/367 ,  H04B1/3838

Abstract: According to various embodiments, an electronic device comprises: a communication processor; at least one radio frequency integrated circuit (RFIC) connected to the communication processor; and a plurality of antennas, each of which is connected to the at least one RFIC through at least one radio frequency front-end (RFFE) circuit and configured to transmit a signal corresponding to at least one communication network, wherein the communication processor may identify information related to strength of a reception signal received through each of the plurality of antennas, identify the maximum transmittable power set corresponding to a transmission path for each of the plurality of antennas, and control the electronic device such that a transmission signal to be transmitted through at least one antenna selected from among the plurality of antennas at least based on the identified information related to the strength of the reception signal and maximum transmittable power.

公开(公告)号：US20230185754A1

公开(公告)日：2023-06-15

申请号：US17899883

申请日：2022-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eunseok SHIN ,  Woochul JUNG ,  Jungho KO ,  Myoungbo KWAK ,  Jaewoo PARK ,  Sunjae LIM ,  Junghwan CHOI

IPC: G06F13/42 ,  H03M9/00

CPC classification number: G06F13/4204 ,  H03M9/00 ,  G06F13/4282 ,  H03K17/6871

Abstract: A parallel-to-serial interface circuit includes an equalizer to delay odd data by a half period and sequentially generate odd pre data, odd main data, and odd post data, and delay even data by a half period and sequentially generate even pre data, even main data, and even post data, a final parallel-to-serial converter to sequentially and alternately select the even pre data and the odd pre data to generate pre data, sequentially and alternately select inverted odd main data and inverted even main data to generate inverted main data, and sequentially and alternately select the even post data and the odd post data to generate post data, and a driver to drive the pre data to generate a pre data level, drive the inverted main data to generate an inverted main data level, and drive the post data to generate a post data level.

公开(公告)号：US20230153571A1

公开(公告)日：2023-05-18

申请号：US17887216

申请日：2022-08-12

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Jun-Woo JANG ,  Jaewoo PARK ,  Faaiz ASIM ,  Jongeun LEE

IPC: G06N3/04 ,  G06N3/063

CPC classification number: G06N3/04 ,  G06N3/063

Abstract: A quantization method of a neural network, and an apparatus for performing the quantization method are provided. The quantization method includes obtaining parameters of the neural network, quantizing the parameters using a quantization scheme in which at least one positive quantization level and at least one negative quantization level symmetric to each other by excluding zero from quantization levels, and outputting the quantized parameters.

公开(公告)号：US20220068332A1

公开(公告)日：2022-03-03

申请号：US17344610

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sucheol LEE ,  Jaewoo PARK ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C7/22 ,  G11C7/10 ,  H03K19/017 ,  H03K19/1776 ,  H03K19/17736

Abstract: A memory device includes a memory cell array and a data input and output circuit configured to output a data signal (DQ signal) including data read from the memory cell array and a data strobe signal (DQS signal) including a toggle pattern associated with an operating condition of the memory device based on n-level pulse amplitude modulation (PAMn), wherein n is an integer greater than or equal to 4.

公开(公告)号：US20250027496A1

公开(公告)日：2025-01-23

申请号：US18906413

申请日：2024-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonhyung KIM ,  Munseong KWON ,  Jaewoo PARK

IPC: F04C18/344 ,  F25B31/02

Abstract: A rotary compressor includes: a case; a cylinder inside the case and has an internal space, and which includes a rolling piston configured to eccentrically rotate in the internal space, a vane in contact with the rolling piston such that while the vane is in contact with the rolling piston, the internal space of the cylinder is divided into a suction chamber and a compression chamber, a suction port to allow refrigerant to flow to the suction chamber, and a discharge port to allow the refrigerant to be discharged the compression chamber; a drive device that includes a rotation shaft connected to the rolling piston and a motor configured to rotate the rotation shaft; and a valve member that is fixed to a side surface of the vane and selectively opens and closes the discharge port as the vane reciprocates back and forth.

公开(公告)号：US20240250689A1

公开(公告)日：2024-07-25

申请号：US18494340

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongmin KO ,  Jaewoo PARK ,  Myoungbo KWAK ,  Jueon KIM ,  Junghwan CHOI

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: An analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) configured to receive an input signal and a first clock signal from an external source and to output a second clock signal and a digital output signal, a decision counter configured to increment a decision count value each time when the second clock signal received from the analog-to-digital converter is applied to the decision counter, a voltage control logic configured to output a control signal based on a result of comparing the decision count value with a reference count value, and a regulator configured to output an operation voltage, wherein the ADC is configured to adjust the cycle of the second clock signal, and the voltage control logic is configured to control the regulator to output a corrected operating voltage via the control signal.

公开(公告)号：US20240056162A1

公开(公告)日：2024-02-15

申请号：US18446814

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemoon CHA ,  Minhwan JEON ,  Jaewoo PARK ,  Yeonjoo LEE

IPC: H04B7/08 ,  H04B7/06

CPC classification number: H04B7/0814 ,  H04B7/0608

Abstract: According to an embodiment, an electronic device may comprise: at least one communication processor, an RF circuitry connected to the at least one communication processor, and a plurality of antennas connected to the RF circuitry. The at least one communication processor may be configured to, based on identifying a folding state of the electronic device being an open state, control the RF circuitry to provide a first RF signal corresponding to a first frequency band to a first antenna among the plurality of antennas. The at least one communication processor may be configured to, based on identifying the folding state of the electronic device being a closed state, identify whether the electronic device is gripped. The at least one communication processor may be configured to control the RF circuitry to provide a second RF signal corresponding to the first frequency band to a second antenna different from the first antenna among the plurality of antennas, based on identifying that the electronic device is gripped.