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    ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND OPERATING METHOD OF THE SAME
    1.
    发明公开
    ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND OPERATING METHOD OF THE SAME 审中-公开

    公开(公告)号：US20240250689A1

    公开(公告)日：2024-07-25

    申请号：US18494340

    申请日：2023-10-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongmin KO ,  Jaewoo PARK ,  Myoungbo KWAK ,  Jueon KIM ,  Junghwan CHOI

    IPC: H03M1/06

    CPC classification number: H03M1/0604

    Abstract: An analog-to-digital conversion circuit includes an analog-to-digital converter (ADC) configured to receive an input signal and a first clock signal from an external source and to output a second clock signal and a digital output signal, a decision counter configured to increment a decision count value each time when the second clock signal received from the analog-to-digital converter is applied to the decision counter, a voltage control logic configured to output a control signal based on a result of comparing the decision count value with a reference count value, and a regulator configured to output an operation voltage, wherein the ADC is configured to adjust the cycle of the second clock signal, and the voltage control logic is configured to control the regulator to output a corrected operating voltage via the control signal.

    TRANSMITTER FOR ULTRA-HIGH SPEED AND STORAGE DEVICE INCLUDING THE SAME
    2.
    发明公开
    TRANSMITTER FOR ULTRA-HIGH SPEED AND STORAGE DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240168091A1

    公开(公告)日：2024-05-23

    申请号：US18325162

    申请日：2023-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ikjin JO ,  Jaewoo PARK ,  Jueon KIM ,  Myoungbo KWAK ,  Junghwan CHOI

    IPC: G01R31/317 ,  G01R31/319

    CPC classification number: G01R31/31727 ,  G01R31/31726 ,  G01R31/31926

    Abstract: A transmitter includes a data generator, a serializer, a transmission driver and a feedback circuit. The data generator generates a retimed data signal and retimed test data by adjusting a delay amount of each of an input data signal and a test data based on adjusted clock signals. The serializer generates a serial data signal by serializing the retimed data signal based on multi-phase clock signals. The transmission driver generates an output data signal based on the serial data signal and transmits the output data signal through a channel. The feedback circuit detects the setup margin and the hold margin of the retimed test data through a separate path different from a path of the retimed data signal and generates the adjusted clock signals by adjusting delay amounts of the multi-phase clock signals based on the detected setup margin and hold margin of the retimed test data.

    VOLTAGE REGULATOR AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    3.
    发明申请
    VOLTAGE REGULATOR AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权

    公开(公告)号：US20220404852A1

    公开(公告)日：2022-12-22

    申请号：US17577201

    申请日：2022-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woochul JUNG ,  Myoungbo KWAK ,  Jaewoo PARK ,  Eunseok SHIN ,  Junhan CHOI

    IPC: G05F1/575 ,  G11C5/14 ,  G11C8/18 ,  G11C8/10

    Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME
    5.
    发明申请
    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230045744A1

    公开(公告)日：2023-02-09

    申请号：US17709853

    申请日：2022-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinook JUNG ,  Jaewoo PARK ,  Junhan CHOI ,  Myoungbo KWAK ,  Junghwan CHOI

    IPC: G05F1/575 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4076

    Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

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