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Patent Agency Ranking
公开(公告)号：US11669773B2
公开(公告)日：2023-06-06
申请号：US16915786
申请日：2020-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungju Kim , Hyojin Choi , In Huh , Jeonghoon Ko , Changwook Jeong , Younsik Park , Joonwan Chai
IPC: G06N20/00 , G06F9/30 , G06F9/38 , G06F30/3308 , G06F18/214
CPC classification number: G06N20/00 , G06F9/30036 , G06F9/3879 , G06F18/214 , G06F30/3308
Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.
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公开(公告)号：US11733603B2
公开(公告)日：2023-08-22
申请号：US17180984
申请日：2021-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehoon Kim , Jaeho Jeong , Jeonghoon Ko , Jongwon Kim , Yejin Jeong , Changwook Jeong
IPC: G03F1/36 , H01L21/027 , G03F7/20 , G03F7/00
CPC classification number: G03F1/36 , G03F7/70441 , G03F7/70625 , H01L21/027
Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.
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公开(公告)号：US20210405521A1
公开(公告)日：2021-12-30
申请号：US17180984
申请日：2021-02-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taehoon Kim , Jaeho Jeong , Jeonghoon Ko , Jongwon Kim , Yejin Jeong , Changwook Jeong
IPC: G03F1/36 , G03F7/20 , H01L21/027
Abstract: A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.
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公开(公告)号：US20210117193A1
公开(公告)日：2021-04-22
申请号：US16915786
申请日：2020-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungju Kim , Hyojin Choi , In Huh , Jeonghoon Ko , Changwook Jeong , Younsik Park , Joonwan Chai
Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.
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公开(公告)号：US10650910B2
公开(公告)日：2020-05-12
申请号：US16249543
申请日：2019-01-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Changwook Jeong , Sanghoon Myung , Min-Chul Park , Jeonghoon Ko , Jisu Ryu , Hyunjae Jang , Hyungtae Kim , Yunrong Li , Min Chul Jeon
Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.
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