公开(公告)号：US20240202424A1

公开(公告)日：2024-06-20

申请号：US18335428

申请日：2023-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichang SIM ,  Ohhun KWON ,  Hyuckjoon KWON ,  Bok-Yeon WON

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A computing device separates a first target layer including a plurality of target patterns from an original design layout, shifts the plurality of target patterns in the first target layer based on misalignment values at positions of the plurality of target patterns to generate a second target layer, and combines the second target layer with the original design layout from which the first target layer is separated to generate a corrected design layout.

公开(公告)号：US20250070022A1

公开(公告)日：2025-02-27

申请号：US18634325

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyun LEE ,  Hyejin KIM ,  Yonghyeok SON ,  Jichang SIM ,  Joo-Sung LEE ,  Yujin CHO

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

Abstract: A semiconductor device may include a substrate including a cell array region, a core region, and a peripheral circuit region, a core circuit wiring on the core region of the substrate, a core signal wiring overlapping the core circuit wiring, and a contact plug between the core circuit wiring and the core signal wiring. The contact plug may connect the core circuit wiring to the core signal wiring. A positional relationship between the core signal wiring and the contact plug may be different depending on distance from the peripheral circuit region.

公开(公告)号：US20230229073A1

公开(公告)日：2023-07-20

申请号：US18048205

申请日：2022-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Cheolhwan KIM ,  Jichang SIM ,  Jongmin LEE ,  Sangeun GO ,  Ohhun KWON ,  Hyuckjoon KWON

IPC: G03F1/36 ,  G03F1/70

CPC classification number: G03F1/36 ,  G03F1/70

Abstract: In a method of correcting a design layout of a semiconductor device, misaligned values of a portion of points of a target pattern of each of a plurality of regions of interest in a semiconductor device fabricated based on an original layout are measured, misaligned values of unmeasured points of the target pattern are estimated by using an artificial neural network trained based on the measured misaligned values of the portion of points, and a target layout of the semiconductor device is generated by using the estimated misaligned values.