公开(公告)号：US10825862B2

公开(公告)日：2020-11-03

申请号：US16394139

申请日：2019-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghyun Cho ,  You-Jin Jung ,  Masayuki Terai ,  Jinchan Yun

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance memory device includes: a substrate including a peripheral region and a core region, the core region including a far region spaced apart from the peripheral region and a near region between the far region and the peripheral region; first conductive lines disposed on the substrate and extending in a first direction; second conductive lines disposed on the first conductive lines and extending in a second direction intersecting the first direction, and memory cells disposed between the first and second conductive lines on the core region. The memory cells include a near memory cell disposed on the near region, and a far memory cell disposed on the far region, wherein a resistance or threshold voltage of the near memory cell, controlling connection of each of the memory cells to a corresponding one of the second conductive lines, is different from that of the far memory cell.

公开(公告)号：US20240321960A1

公开(公告)日：2024-09-26

申请号：US18613324

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinchan Yun ,  Sungil Park ,  Jaehyun Park ,  Dongkyu Lee ,  Kyuman Hwang

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A multi-stack semiconductor device includes a substrate, a device isolation layer, first channels, first gate lines covering the first channel, extending in a second horizontal direction, and spaced apart from each other in the first horizontal direction, first source/drain areas arranged on both sides of each of the first channels in the first horizontal direction, a second channel arranged apart from the first gate line in the vertical direction over any one of the first gate lines, a second gate line, second source/drain areas, a third channel arranged apart from the second gate line in the vertical direction over the second gate line, a third gate line, third source/drain areas, and a first lower source/drain contact extending in the vertical direction and connected to each of the first source/drain area, the second source/drain area, and the third source/drain area.

公开(公告)号：US20250151388A1

公开(公告)日：2025-05-08

申请号：US18738621

申请日：2024-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Jae Hyun Park ,  Jinchan Yun ,  Daihong Huh

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device incudes: a plurality of lower channel patterns apart from each other; a plurality of upper channel patterns spaced apart from each other on the plurality of lower channel patterns; a gate structure surrounding the plurality of lower channel patterns and the plurality of upper channel patterns; a lower source/drain trench positioned on at least one side of the plurality of lower channel patterns; an upper source/drain trench positioned on at least one side of the plurality of upper channel patterns; a lower source/drain pattern positioned within the lower source/drain trench; and an upper source/drain pattern including first upper source/drain layers positioned on opposite sidewalls of the upper source/drain trench, and a second upper source/drain layer positioned between the first upper source/drain layers, in which the first upper source/drain layer does not cover at least a portion of the bottom surface of the upper source/drain trench.

公开(公告)号：US20250040206A1

公开(公告)日：2025-01-30

申请号：US18583500

申请日：2024-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dahye Kim ,  Jinchan Yun ,  Daihong Huh ,  Jaehyun Park

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A semiconductor device is described. The device includes lower and upper channel layers over an active region on a substrate. The device further includes a middle insulating structure disposed between the lower and the upper channels. The device includes gate structures surrounding the channel layers, lower and upper source/drain regions disposed on the active region on at least one side of the gate structures. Between the lower and upper source/drain regions is a barrier structure. The lower and upper source/drain regions may each fill a lower recess region or an upper recess region, respectively. These recess regions are defined by the respective channel layers, the gate structures, and by the barrier structure. The side surface slopes within the upper and the lower recess regions may vary and the side surface slopes of each of the recess regions may be different from each other.

公开(公告)号：US20240282864A1

公开(公告)日：2024-08-22

申请号：US18432351

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Lee ,  Sungil Park ,  Jaehyun Park ,  Jinwook Yang ,  Jinchan Yun ,  Cheoljin Yun ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit semiconductor device with three dimensional transistors includes two gate-all-around transistors or multi-bridge channel field effect transistors may be vertically stacked to reduce unit area. The two stacked transistors may be separated by an isolation insulating layer. The two stacked transistors may be positioned on two opposite sides of the isolation insulating layer, with the structure of the two stacked transistors positioned in an opposite manner. According to embodiments of the present disclosure, metal wiring layers may be connected to the two stacked transistors at their far ends, away from the isolation insulating layer. A method for manufacturing an integrated circuit semiconductor device according to the present disclosure is described. Accordingly, aspects described herein may result in reduced unit area and easy manufacture of metal wiring layer connected to the transistors.