公开(公告)号：US20180122845A1

公开(公告)日：2018-05-03

申请号：US15602185

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hyung KIM ,  Seokho KIM ,  SungHyup KIM ,  Jaegeun KIM ,  Taeyeong KIM

IPC: H01L27/146

CPC classification number: H01L27/1469 ,  H01L21/2007 ,  H01L24/01 ,  H01L24/03 ,  H01L24/04 ,  H01L24/74 ,  H01L24/80 ,  H01L27/14634 ,  H01L27/14683 ,  H01L27/14687

Abstract: Disclosed are a substrate bonding apparatus and a method of manufacturing a semiconductor device. The substrate bonding apparatus comprises vacuum pumps, a first chuck engaged with the vacuum pumps and adsorbing a first substrate at vacuum pressure of the vacuum pumps, and a pushing unit penetrating a center of the first chuck and pushing the first substrate away from the first chuck. The first chuck comprises adsorption sectors providing different vacuum pressures in an azimuth direction to the first substrate.

公开(公告)号：US20230012525A1

公开(公告)日：2023-01-19

申请号：US17692953

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-Heung KIM ,  Jun Hyung KIM ,  Chang-Yong LEE ,  Sang Uhn CHA ,  Kyung-Soo HA

IPC: G06F11/10 ,  G06F11/07 ,  G06F3/06

Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

公开(公告)号：US20140264936A1

公开(公告)日：2014-09-18

申请号：US14201307

申请日：2014-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Youl CHOI ,  Jun Hyung KIM ,  Byung Hyun LEE

IPC: H01L23/48

CPC classification number: G11C5/063 ,  G11C7/10 ,  G11C2207/105 ,  H01L25/0657 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package including a first connection terminal group configured to receive a first signal group from the outside of the semiconductor package, a second connection terminal group configured to transmit a second signal group to the outside, a first chip connected to the first connection terminal group, and a second chip connected to the second connection terminal group and configured to receive the first and second signal groups from the first chip. Degradation of the performance of the semiconductor package, caused by the differences between signal delay times in a plurality of chips therein may be minimized.

Abstract translation: 一种半导体封装，包括被配置为从所述半导体封装的外部接收第一信号组的第一连接端子组，被配置为向外部发送第二信号组的第二连接端子组，连接到所述第一连接端子组的第一芯片 以及连接到第二连接端子组并被配置为从第一芯片接收第一和第二信号组的第二芯片。 由于其中的多个芯片中的信号延迟时间之间的差异引起的半导体封装的性能的降低可能被最小化。

公开(公告)号：US20190206460A1

公开(公告)日：2019-07-04

申请号：US16032768

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong IL O ,  Jun Hyung KIM ,  Kyo Min SOHN

IPC: G11C8/18 ,  G11C8/12 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/18

Abstract: A memory device can include a plurality of memory banks coupled to an input/output bus and a memory controller coupled to the plurality of memory banks. The memory controller can be configured to control operations of the plurality of memory banks, where each of the plurality of memory banks can include a bank array including a plurality of memory cells configured to store data, a latch circuit coupled to the input/output bus, where the latch circuit can be configured to store target data received via the input/output bus to provide stored target data, and a comparison circuit coupled to the latch circuit, where the comparison circuit can be configured to compare stored data output by the bank array with the stored target data to provide result data to the memory controller.