公开(公告)号：US20140061890A1

公开(公告)日：2014-03-06

申请号：US14013714

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Do Lee ,  Taewoo Kang ,  Donghan Kim ,  JongBo Shim ,  Yang-hoon Ahn ,  SeokWon Lee ,  Dae-young Choi

IPC: H01L23/34

CPC classification number: H01L23/34 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49827 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure.

Abstract translation: 半导体封装可以包括安装在基板上的半导体芯片，保护半导体芯片并具有与半导体芯片的顶表面大致相同高度的顶表面的模制部件，模制部件上的热排出部分和半导体 散热部和模制部之间以及排热部和半导体芯片之间的粘接部。 散热部与粘接部之间的界面具有凹凸结构。

公开(公告)号：US08623743B2

公开(公告)日：2014-01-07

申请号：US13741466

申请日：2013-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Do Lee ,  JongKook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。