公开(公告)号：US20140061890A1

公开(公告)日：2014-03-06

申请号：US14013714

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Do Lee ,  Taewoo Kang ,  Donghan Kim ,  JongBo Shim ,  Yang-hoon Ahn ,  SeokWon Lee ,  Dae-young Choi

IPC: H01L23/34

CPC classification number: H01L23/34 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/42 ,  H01L23/4334 ,  H01L23/49827 ,  H01L25/0652 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure.

Abstract translation: 半导体封装可以包括安装在基板上的半导体芯片，保护半导体芯片并具有与半导体芯片的顶表面大致相同高度的顶表面的模制部件，模制部件上的热排出部分和半导体 散热部和模制部之间以及排热部和半导体芯片之间的粘接部。 散热部与粘接部之间的界面具有凹凸结构。

公开(公告)号：US10651074B2

公开(公告)日：2020-05-12

申请号：US15595948

申请日：2017-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Hwan Kim ,  Taewoo Kang ,  Byung Lyul Park ,  Hyungjun Jeon

IPC: H01L21/683 ,  B65G47/91 ,  C23C16/458 ,  H01L21/67 ,  H01L21/687

Abstract: A substrate processing apparatus may include a substrate jig device and a transfer unit, which is configured to hold a substrate in a non-contact state and move the substrate toward the substrate jig device. The substrate jig device may include a supporter, which is configured to support an edge of the substrate and have an opening, a first suction part, which overlaps with a center region of the opening and is configured to move in a first direction, and a plurality of second suction parts, which overlap with an edge region of the opening and are configured to move toward the opening. Here, the first direction may be a direction passing through the opening.

公开(公告)号：US20230144388A1

公开(公告)日：2023-05-11

申请号：US17983145

申请日：2022-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungkyu KWON ,  Taewoo Kang ,  Taehun Kim

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/18 ,  H01L23/562 ,  H01L23/367 ,  H01L23/42 ,  H01L2224/16227 ,  H01L24/16 ,  H01L2224/32225 ,  H01L24/32 ,  H01L2224/73204 ,  H01L24/73 ,  H01L2224/73253 ,  H01L2224/33181 ,  H01L24/33

Abstract: A semiconductor package includes a package substrate including a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, semiconductor chips mounted on the first to third chip mounting areas, a first stiffener mounted on the package substrate to separate the first chip mounting area from the second chip mounting area, and a second stiffener mounted on the package substrate to separate the second chip mounting area from the third chip mounting area.

公开(公告)号：US11715697B2

公开(公告)日：2023-08-01

申请号：US17096107

申请日：2020-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungbum Kim ,  Taewoo Kang ,  Jaewon Choi

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L23/3107 ,  H01L23/49816

Abstract: A semiconductor package may include a lower package including a first substrate, a first semiconductor chip on the first substrate, and a first molding portion on the first substrate to cover the first semiconductor chip, an interposer substrate on the first semiconductor chip, a supporting portion between the interposer substrate and the first substrate to support the interposer substrate, a connection terminal connecting the interposer substrate to the first substrate, and an upper package on the interposer substrate. The upper package may include a second substrate, a second semiconductor chip on the second substrate, and a second molding portion on the second substrate to cover the second semiconductor chip.