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公开(公告)号:US20140061890A1
公开(公告)日:2014-03-06
申请号:US14013714
申请日:2013-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung-Do Lee , Taewoo Kang , Donghan Kim , JongBo Shim , Yang-hoon Ahn , SeokWon Lee , Dae-young Choi
IPC: H01L23/34
CPC classification number: H01L23/34 , H01L23/3128 , H01L23/3142 , H01L23/367 , H01L23/42 , H01L23/4334 , H01L23/49827 , H01L25/0652 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/73253 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/15311 , H01L2924/18161
Abstract: A semiconductor package may include a semiconductor chip mounted on a substrate, a molding part protecting the semiconductor chip and having a top surface at a substantially equal height to a top surface of the semiconductor chip, a heat exhausting part on the molding part and the semiconductor chip, and an adhesive part between the heat exhausting part and the molding part and between the heat exhausting part and the semiconductor chip. An interface between the heat exhausting part and the adhesive part has a concave-convex structure.
Abstract translation: 半导体封装可以包括安装在基板上的半导体芯片,保护半导体芯片并具有与半导体芯片的顶表面大致相同高度的顶表面的模制部件,模制部件上的热排出部分和半导体 散热部和模制部之间以及排热部和半导体芯片之间的粘接部。 散热部与粘接部之间的界面具有凹凸结构。
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公开(公告)号:US09112062B2
公开(公告)日:2015-08-18
申请号:US13974254
申请日:2013-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: JiSun Hong , Hyunki Kim , JongBo Shim , SeokWon Lee , Kyoungsei Choi
CPC classification number: H01L24/97 , H01L21/561 , H01L23/3128 , H01L23/3135 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2224/48227 , H01L2924/00012 , H01L2224/81 , H01L2924/00
Abstract: A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.
Abstract translation: 一种半导体器件包括:第一半导体封装,包括第一模具部件,包括第二模具部件的第二半导体封装,被配置为使第一和第二半导体封装彼此电连接的连接图案;以及第一和第二半导体封装之间的模制图案 半导体封装。 模制图案延伸以覆盖仅第二半导体封装的侧壁的至少一部分。
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