公开(公告)号：US08623743B2

公开(公告)日：2014-01-07

申请号：US13741466

申请日：2013-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Do Lee ,  JongKook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。

公开(公告)号：US10770383B2

公开(公告)日：2020-09-08

申请号：US16413757

申请日：2019-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hohyeuk Im

IPC: H01L23/34 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.

公开(公告)号：US10573588B2

公开(公告)日：2020-02-25

申请号：US15987976

申请日：2018-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hohyeuk Im

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/528

Abstract: A package substrate and a semiconductor package are provided. The package substrate including a substrate body having a first surface on which a semiconductor chip is mounted and a second surface opposite to the first surface, and a conductive pad at the first surface, the conductive pad elongated in a first direction, the conductive pad including a plurality of sub-bar patterns spaced apart from each other in the first direction may be provided.

公开(公告)号：US10438879B2

公开(公告)日：2019-10-08

申请号：US15252519

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hohyeuk Im

IPC: H01L23/34 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.

公开(公告)号：US20130130472A1

公开(公告)日：2013-05-23

申请号：US13741466

申请日：2013-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Do LEE ,  Jongkook Kim ,  SeokWon Lee ,  Jaesik Lee ,  Hohyeuk Im ,  Su-Min Park

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.

Abstract translation: 提供了一种半导体芯片。 半导体芯片包括包括主芯片区域和围绕主芯片区域的划线通道区域的半导体衬底。 绝缘层设置在半导体衬底上。 保护环设置在划线区域的绝缘层中。 防护环围绕主芯片区域的至少一部分。 保护环的脆性大于绝缘层的脆性。

公开(公告)号：US10553529B2

公开(公告)日：2020-02-04

申请号：US15252519

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hohyeuk Im

IPC: H01L23/34 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.

公开(公告)号：US20190273039A1

公开(公告)日：2019-09-05

申请号：US16413757

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hohyeuk Im

IPC: H01L23/498 ,  H01L25/065

Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.

公开(公告)号：US09252031B2

公开(公告)日：2016-02-02

申请号：US14493379

申请日：2014-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hohyeuk Im ,  Jongkook Kim ,  Gowoon Seong ,  SeokWon Lee ,  Byoungwook Jang ,  Eunseok Cho

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05599

Abstract: Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.

Abstract translation: 提供了一种半导体封装，其包括下封装，下封装上的插入件和插入件上的上封装。 下封装可以包括下封装衬底，下封装衬底上的下半导体芯片和下半导体芯片上的下传热层。 插入器可以包括插入器基板，分别由插入器基板的凹入的底部和顶部表面限定的第一和第二传热开口，设置在第二传热开口中的上插入件传热垫，以及上部热 - 转移层，设置在上部插入件传热垫上。 上封装可以包括上封装衬底，上封装传热垫，其可以设置在由上封装衬底的凹陷底表面限定的第三传热开口中，以及设置在上封装衬底上的上半导体芯片 封装衬底。