公开(公告)号：US20210327839A1

公开(公告)日：2021-10-21

申请号：US17361588

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon HAN ,  Dong-Wan KIM ,  Dongho KIM ,  Jaewon SEO

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/67

Abstract: A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

公开(公告)号：US20210305115A1

公开(公告)日：2021-09-30

申请号：US17206295

申请日：2021-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjung CHOI ,  Jung-Hoon HAN ,  Jiho KIM ,  Young-Yong BYUN ,  Yeonjin LEE ,  Jihoon CHANG

IPC: H01L23/31 ,  H01L23/528

Abstract: A semiconductor device including a substrate including a chip region and an edge region; integrated circuit elements on the chip region; an interlayer insulating layer covering the integrated circuit elements; an interconnection structure on the interlayer insulating layer and having a side surface on the edge region; a first and second conductive pattern on the interconnection structure, the first and second conductive patterns being electrically connected to the interconnection structure; a first passivation layer covering the first and second conductive patterns and the side surface of the interconnection structure; and a second passivation layer on the first passivation layer, wherein the second passivation layer includes an insulating material different from the first passivation layer, and, between the first and second conductive patterns, the second passivation layer has a bottom surface that is located at a vertical level lower than a top surface of the first conductive pattern.

公开(公告)号：US20200058543A1

公开(公告)日：2020-02-20

申请号：US16420328

申请日：2019-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon HAN ,  Seokhwan KIM ,  Joodong KIM ,  Junyong NOH ,  Jaewon SEO

IPC: H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

公开(公告)号：US20230043650A1

公开(公告)日：2023-02-09

申请号：US17964244

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20210305153A1

公开(公告)日：2021-09-30

申请号：US17153963

申请日：2021-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihoon CHANG ,  Jimin CHOI ,  Yeonjin LEE ,  Hyeon-Woo JANG ,  Jung-Hoon HAN

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

公开(公告)号：US20170256476A1

公开(公告)日：2017-09-07

申请号：US15443259

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan Kim ,  Jung-Hoon HAN ,  Dong-Sik PARK

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/5384 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

公开(公告)号：US20230071440A1

公开(公告)日：2023-03-09

申请号：US17737115

申请日：2022-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ah Rang CHOI ,  Chan-Sic YOON ,  Jung-Hoon HAN ,  Gyu Hyun KIL ,  Weon Hong KIM ,  Doo San BACK

IPC: H01L27/108

Abstract: Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.

公开(公告)号：US20220139927A1

公开(公告)日：2022-05-05

申请号：US17371873

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hoon CHANG ,  Jung-Hoon HAN ,  Ji Seok HONG ,  Dong-Sik PARK

IPC: H01L27/108 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.

公开(公告)号：US20220005730A1

公开(公告)日：2022-01-06

申请号：US17482796

申请日：2021-09-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon HAN ,  Seokhwan KIM ,  Joodong KIM ,  Junyong NOH ,  Jaewon SEO

IPC: H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a semiconductor substrate including a chip region and an edge region around the chip region; a lower dielectric layer and an upper dielectric layer on the semiconductor substrate; a redistribution chip pad that penetrates the upper dielectric layer on the chip region and is connected a chip pad; a process monitoring structure on the edge region; and dummy elements in the edge region and having an upper surface lower than an upper surface of the upper dielectric layer.

公开(公告)号：US20210143086A1

公开(公告)日：2021-05-13

申请号：US17152012

申请日：2021-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Wan KIM ,  Jung-Hoon HAN ,  Dong-Sik PARK

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768

Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.