公开(公告)号：US20190130953A1

公开(公告)日：2019-05-02

申请号：US15997964

申请日：2018-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yun LEE ,  Joon Soo KWON ,  Byung Soo KIM ,  Su-Yong KIM ,  Sang-Soo PARK ,  Il Han PARK ,  Kang-Bin LEE ,  Jong-Hoon LEE ,  Na-Young CHOI

IPC: G11C8/08 ,  G06F3/06 ,  G11C16/12 ,  G11C5/14 ,  G11C16/14 ,  G11C29/02

Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

公开(公告)号：US20230197161A1

公开(公告)日：2023-06-22

申请号：US18173730

申请日：2023-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN JOE ,  Kang-Bin LEE

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L24/05 ,  H10B41/27 ,  H10B43/27 ,  H01L2924/14511 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.

公开(公告)号：US20160379716A1

公开(公告)日：2016-12-29

申请号：US15259765

申请日：2016-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Wan NAM ,  Kang-Bin LEE ,  Junghoon PARK

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3459 ,  H01L27/1157 ,  H01L27/11582

Abstract: An operating method of a nonvolatile memory, which includes a plurality of cell strings, each cell string having a plurality of memory cells and a string selection transistor stacked on a substrate, includes detecting threshold voltages of the string selection transistors of the plurality of cell strings; adjusting voltages to be supplied to the string selection transistors according to the detected threshold voltages; and applying the adjusted voltages to the string selection transistors to select or unselect the plurality of cell strings during a programming operation.