公开(公告)号：US20170365361A1

公开(公告)日：2017-12-21

申请号：US15696794

申请日：2017-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uhn CHA ,  Hoi-Ju CHUNG ,  Jong-Pil SON ,  Kwang-II PARK ,  Seong-Jin JANG

IPC: G11C29/52 ,  G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C11/15 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C11/15 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/702 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

公开(公告)号：US20240086603A1

公开(公告)日：2024-03-14

申请号：US18511605

申请日：2023-11-16

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： In HUH ,  Jeong-hoon KO ,  Hyo-jin CHOI ,  Seung-ju KIM ,  Chang-wook JEONG ,  Joon-wan CHAI ,  Kwang-II PARK ,  Youn-sik PARK ,  Hyun-sun PARK ,  Young-min OH ,  Jun-haeng LEE ,  Tae-ho LEE

IPC: G06F30/33 ,  G06N3/08

CPC classification number: G06F30/33 ,  G06N3/08

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

公开(公告)号：US20160064056A1

公开(公告)日：2016-03-03

申请号：US14798164

申请日：2015-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SU-A KIM ,  Dae-Sun KIM ,  Dae-Jeong KIM ,  Sung-Min RYU ,  Kwang-II PARK ,  Chul-Woo PARK ,  Young-Soo SOHN ,  Jae-Youn YOUN

IPC: G11C8/08 ,  G11C7/02

CPC classification number: G11C8/08 ,  G11C5/025 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4097

Abstract: A semiconductor memory device includes a memory cell array, sub word-line drivers and power selection switches. The memory cell array includes memory cell rows coupled to word lines. The sub word line drivers are coupled to the word lines. The power selection switches are coupled to the sub word-line drivers. Each power selection switch controls a deactivation voltage level of a first word-line activated from the word-lines and an off-voltage level of a second word line adjacent to the first word line so that the deactivation voltage level and the off-voltage level have at least one of a ground voltage, a first negative voltage and a second negative voltage. The ground voltage, the first negative voltage and the second negative voltage have different voltage levels from each other.

Abstract translation: 半导体存储器件包括存储单元阵列，子字线驱动器和功率选择开关。 存储单元阵列包括耦合到字线的存储单元行。 子字线驱动器耦合到字线。 电源选择开关耦合到子字线驱动器。 每个电源选择开关控制从字线激活的第一字线的去激活电压电平和与第一字线相邻的第二字线的截止电压电平，使得去激活电压电平和截止电压电平 具有接地电压，第一负电压和第二负电压中的至少一个。 接地电压，第一负电压和第二负电压彼此具有不同的电压电平。