公开(公告)号：US20150009742A1

公开(公告)日：2015-01-08

申请号：US14223867

申请日：2014-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang KANG ,  Jung-Bum SHIN ,  Chan-Yong LEE

IPC: G11C14/00 ,  G11C5/14 ,  G11C17/16

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: Provided is a semiconductor memory device with improved fuse sensing reliability during a slow power-up operation. The semiconductor memory device may include a memory cell array including a normal memory cell array and a spare memory cell array; an anti-fuse circuit supplied with a first voltage and configured to store fail address information associated with a defective memory cell in the normal memory cell array and configured to sense the fail address information in response to a clock signal applied during a power-up period; and a fuse read circuit including a clock generator supplied with a second voltage, the fuse read circuit configured to detect respective levels of the first and second voltages during the power-up period to generate the clock signal and to read the sensed fail address information from the anti-fuse circuit in response to the clock signal.

Abstract translation: 提供了在慢速上电操作期间具有改进的熔丝感测可靠性的半导体存储器件。 半导体存储器件可以包括包括正常存储单元阵列和备用存储单元阵列的存储单元阵列; 提供有第一电压并被配置为存储与正常存储单元阵列中的有缺陷的存储器单元相关联的故障地址信息的反熔丝电路，并且被配置为响应于在上电周期期间施加的时钟信号来感测故障地址信息 ; 以及包括提供有第二电压的时钟发生器的熔丝读取电路，所述熔丝读取电路被配置为在上电周期期间检测第一和第二电压的相应电平，以产生时钟信号，并从 反熔丝电路响应于时钟信号。

公开(公告)号：US20250140751A1

公开(公告)日：2025-05-01

申请号：US18612283

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok LEE ,  Kyu-Chang KANG ,  Kangsub JEONG ,  Dayoung KIM ,  Young Seok PARK

IPC: H01L25/065 ,  G11C11/4091 ,  H01L23/00 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor memory device may include a first chip include a first array matrix and a second array matrix adjacent to each other and including memory cells, and a second chip below the first chip, and including sense amplifiers configured to drive the memory cells, where first cell bit lines are in the first array matrix, and second cell bit lines are in the second array matrix, where first bit lines and first complementary bit lines are below the first array matrix, and second bit lines and second complementary bit lines are below the second array matrix, and where the first bit lines and the second bit lines are connected to the first cell bit lines and the second cell bit lines, respectively, the first complementary bit lines and the second complementary bit lines are connected to the second cell bit lines and first cell bit lines, respectively.

公开(公告)号：US20170213586A1

公开(公告)日：2017-07-27

申请号：US15331970

申请日：2016-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang KANG ,  Hui-Kap YANG

IPC: G11C11/406 ,  G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40603 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091

Abstract: A memory device includes a memory bank, a row selection circuit and a refresh controller. The memory bank includes a plurality of memory blocks, and each memory block includes a plurality of memory cells arranged in rows and columns. The row selection circuit performs an access operation with respect to the memory bank and a hammer refresh operation with respect to a row that is physically adjacent to a row that is accessed intensively. The refresh controller controls the row selection circuit such that the hammer refresh operation is performed during a row active time for the access operation. The hammer refresh operation may be performed efficiently and performance of the memory device may be enhanced by performing the hammer refresh operation during the row active time for the access operation.

公开(公告)号：US20150325316A1

公开(公告)日：2015-11-12

申请号：US14595500

申请日：2015-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang KANG ,  Gil-Su KIM ,  Je-Min RYU ,  Yun-Young LEE ,  Kyo-Min SOHN

IPC: G11C29/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。