公开(公告)号：US20210043639A1

公开(公告)日：2021-02-11

申请号：US16814491

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L27/11582

Abstract: A memory device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder; a cell array region including wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating through the wordlines; and a cell contact region including cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction. Each of the first and second cell contact regions includes first pads having different lengths to each other in the first direction and second pads different from the first pads, and the cell contacts are connected to the wordlines in the first pads. The number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region.

公开(公告)号：US20220352204A1

公开(公告)日：2022-11-03

申请号：US17860618

申请日：2022-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa YUN ,  Chanho Kim ,  Dongku Kang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

公开(公告)号：US20210066281A1

公开(公告)日：2021-03-04

申请号：US16944711

申请日：2020-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong KWON ,  Youngsun MIN ,  Daeseok BYEON ,  Kyunghwa YUN

IPC: H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

公开(公告)号：US20210065801A1

公开(公告)日：2021-03-04

申请号：US16862167

申请日：2020-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong KWON ,  Youngsun MIN ,  Daeseok BYEON ,  Kyunghwa YUN

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

公开(公告)号：US20210036008A1

公开(公告)日：2021-02-04

申请号：US16809059

申请日：2020-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwa YUN ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A vertical memory device is provided. The vertical memory device includes gate electrodes formed on a substrate and spaced apart from each other in a first direction substantially perpendicular to an upper surface of the substrate, the gate electrodes including a first gate electrode and a second gate electrode that is interposed between the first gate electrode and the substrate; a channel extending through the gate electrodes in the first direction; an insulating isolation pattern extending through the first gate electrode in the first direction, and spaced apart from the first gate electrode in a second direction substantially parallel to the upper surface of the substrate; and a blocking pattern disposed on an upper surface, a lower surface and a sidewall of each of the gate electrodes, the sidewall of the gate electrodes facing the channel. The insulating isolation pattern directly contacts the first gate electrode.

公开(公告)号：US20220208784A1

公开(公告)日：2022-06-30

申请号：US17695186

申请日：2022-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20220093629A1

公开(公告)日：2022-03-24

申请号：US17242696

申请日：2021-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Chanho KIM ,  Kyunghwa YUN ,  Dongseong KIM

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device and an electronic system, the semiconductor device including a semiconductor substrate; a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuits; a semiconductor layer on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor layer, the metal structure including first portions extending in a first direction, second portions connected to the first portions and extending in a second direction crossing the first direction, and a via portion vertically extending from at least one of the first and second portions and being connected to the landing pad; and a stack including insulating layers and electrodes vertically and alternately stacked on the metal structure.

公开(公告)号：US20210118861A1

公开(公告)日：2021-04-22

申请号：US16940333

申请日：2020-07-27

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Kyunghwa YUN ,  Chanho KIM ,  Dongku KANG

IPC: H01L25/18 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L25/065 ,  H01L23/00

Abstract: A nonvolatile memory device includes a memory cell region including first metal pads, and a peripheral circuit region including second metal pads. The memory cell region includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly.

公开(公告)号：US20210043641A1

公开(公告)日：2021-02-11

申请号：US17001035

申请日：2020-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwa YUN ,  Pansuk KWAK ,  Chanho KIM ,  Dongku KANG

IPC: H01L27/11573 ,  H01L27/1157 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11524

Abstract: A memory device comprises a peripheral circuit region including a first substrate and circuit elements on the first substrate, the circuit elements including a row decoder, and a memory cell region including a cell array region and a cell contact region, wherein the cell array region includes wordlines, stacked on a second substrate on the peripheral circuit region, and channel structures extending in a direction perpendicular to an upper surface of the second substrate and penetrating the wordlines, wherein the cell contact region includes cell contacts connected to the wordlines and on both sides of the cell array region in a first direction parallel to the upper surface of the second substrate, the cell contacts including a first cell contact region and a second cell contact region, the first and second cell contact regions having different lengths to each other in the first direction, wherein each of the first and second cell contact regions includes first pads having different lengths than each other in the first direction, and second pads different from the first pads, wherein the cell contacts are connected to the wordlines in the first pads, wherein the number of the second pads included in the first cell contact region is greater than the number of the second pads included in the second cell contact region, and wherein the memory cell region includes a first metal pad and the peripheral circuit region includes a second metal pad, and the memory cell region and the peripheral circuit region are vertically connected to each other by the first metal pad and the second metal pad.