公开(公告)号：US20240232012A1

公开(公告)日：2024-07-11

申请号：US18399864

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seongmuk KANG ,  KYUNG-HO LEE ,  MYUNGKYU LEE ,  KI-HEUNG KIM ,  KYOMIN SOHN ,  KIJUN LEE ,  SUNGHYE CHO ,  HYONGRYOL HWANG

IPC: G06F11/10 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C29/42

CPC classification number: G06F11/1068 ,  G11C7/06 ,  G11C7/1078 ,  G11C7/12 ,  G11C29/42

Abstract: A memory device includes an ECC circuit that performs error correction code (ECC) encoding on input data to generate write data, and a memory cell array including a plurality of memory cells that stores the write data. The ECC circuit includes a data splitter that splits the input data into first sub-data and second sub-data, a first ECC encoder that performs ECC encoding on the first sub-data to generate first sub-parity data, a second ECC encoder that performs ECC encoding on the second sub-data to generate second sub-parity data, and a data scrambler that performs a data scrambling operation with respect to the first sub-data, the second sub-data, the first sub-parity data, and the second sub-parity data based on a structure of the memory cell array to generate the write data.

公开(公告)号：US20130283128A1

公开(公告)日：2013-10-24

申请号：US13801297

申请日：2013-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： KIJUN LEE ,  DONG-MIN SHIN ,  KYEONGCHEOL YANG ,  SEUNG-CHAN LIM ,  JUNJIN KONG ,  MYUNGKYU LEE

IPC: G06F11/10 ,  G11C7/10

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/0483 ,  G11C29/56004 ,  G11C29/56008 ,  G11C2211/5641 ,  H03M13/13

Abstract: An operating method of a nonvolatile memory device controller includes generating a code word through polar encoding of information bits, reading a mapping pattern, generating a repeated mapping pattern through iteration of the mapping pattern, and mapping each bit of the code word onto a specific bit of multi-bit data of the nonvolatile memory device, based upon the repeated mapping pattern.

Abstract translation: 非易失性存储器件控制器的操作方法包括通过信息位的极性编码产生代码字，读取映射模式，通过迭代映射模式生成重复映射模式，并将代码字的每一位映射到特定位 的非易失性存储器件的多位数据。

公开(公告)号：US20240370335A1

公开(公告)日：2024-11-07

申请号：US18778475

申请日：2024-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae Kim ,  KIJUN LEE ,  MYUNGKYU LEE ,  YEONGGEOL SONG ,  Jinhoon Jang ,  SUNGHYE CHO ,  Isak Hwang

IPC: G06F11/10

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first coedword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

公开(公告)号：US20240248850A1

公开(公告)日：2024-07-25

申请号：US18416558

申请日：2024-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEHYUN KIM ,  SEONGMUK KANG ,  JIHO KIM ,  KYOMIN SOHN ,  YEONGGEOL SONG ,  KIJUN LEE ,  MYUNGKYU LEE ,  SUKHAN LEE

IPC: G06F12/0891 ,  G06F12/126

CPC classification number: G06F12/0891 ,  G06F12/126

Abstract: A memory system includes a system controller and a memory device. The system controller includes a memory controller configured to transmit a received address to a decoding module, and output, to the host device, decoded data. The decoding module includes a cache device and a decoder. The decoding module is configured to receive the data corresponding to the address from the memory device. The decoding module is configured transmit the data stored in the cache device to the memory controller in response to determining that the data corresponding to the address is stored in the cache device. The decoding module is configured to decode the data corresponding to the address to generate decoded data and store the decoded result in the cache device in response to determining that the data corresponding to the address is not stored in the cache device.

公开(公告)号：US20230420027A1

公开(公告)日：2023-12-28

申请号：US18197084

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUN AE LEE ,  SUNGHYE CHO ,  KIJUN LEE ,  KYOMIN SOHN ,  MYUNGKYU LEE

IPC: G11C11/406

CPC classification number: G11C11/40622 ,  G11C11/40615

Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

公开(公告)号：US20210334033A1

公开(公告)日：2021-10-28

申请号：US17090726

申请日：2020-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHYE CHO ,  KIJUN LEE ,  SUNG-RAE KIM ,  CHANKI KIM ,  YEONGGEOL SONG ,  YESIN RYU ,  JAEYOUN YOUN ,  MYUNGKYU LEE

IPC: G06F3/06

Abstract: A method for reading data from a memory includes; reading a codeword from the memory cells, correcting the errors when a number of errors in the codeword is less than a maximum number of correctable errors, correcting the errors when the number of errors in the codeword is equal to the maximum number of correctable errors and the errors correspond to a same sub-word line, and outputting signal indicating that the errors are an uncorrectable error when the number of errors of the codeword is equal to the maximum number of correctable errors and the errors correspond to different sub-word lines.

公开(公告)号：US20210224156A1

公开(公告)日：2021-07-22

申请号：US16926000

申请日：2020-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHYE CHO ,  KIJUN LEE ,  YEONGGEOL SONG ,  SUNGRAE KIM ,  CHANKI KIM ,  MYUNGKYU LEE ,  SANGUHN CHA

IPC: G06F11/10 ,  H03M13/15 ,  H03M13/00

Abstract: An error correction circuit of a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates, based on a main data, a parity data using an ECC represented by a generation matrix and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device to generate different syndromes based on the read codeword and a parity check matrix which is based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when the single bit error exists in the main data or to correct two bit errors when the two bit errors occur in adjacent two memory cells in the target page.