公开(公告)号：US20210397368A1

公开(公告)日：2021-12-23

申请号：US17328225

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo NAM ,  Sungho SEO ,  Kwanwoo NOH ,  Myungsub SHIN ,  Haesung JUNG

IPC: G06F3/06

Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

公开(公告)号：US20210263550A1

公开(公告)日：2021-08-26

申请号：US17179830

申请日：2021-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F3/06

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20240184480A1

公开(公告)日：2024-06-06

申请号：US18438795

申请日：2024-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwoo NAM ,  Sungho SEO ,  Kwanwoo NOH ,  Myungsub SHIN ,  Haesung JUNG

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F13/385 ,  G06F13/4278

Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

公开(公告)号：US20240085940A1

公开(公告)日：2024-03-14

申请号：US18508479

申请日：2023-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/4291 ,  G11C7/22 ,  G11C16/32 ,  H04L7/0004 ,  H04L7/0008

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20230112284A1

公开(公告)日：2023-04-13

申请号：US18064002

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F3/06 ,  G11C7/22 ,  G11C16/32 ,  G06F1/04 ,  G06F13/42 ,  H04L7/00

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20220113909A1

公开(公告)日：2022-04-14

申请号：US17375328

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myungsub SHIN ,  Sungho SEO ,  Seongyong JANG ,  Haesung JUNG

IPC: G06F3/06

Abstract: An electronic device may include a host device and a storage device which are connected in a universal flash storage standard, wherein the host device may include processing circuitry configured to process a submission queue (SQ) and a completion queue (CQ), wherein the SQ is a processing standby line of a command, and the CQ is a processing standby line of a response received from the storage device, transmit the command to the storage device, store a host command credit in a host command register, the host command credit indicating an estimated command accommodation limit of the storage device, store the response in a response slot, and store a host response credit in a host command register, the host command credit indicating a limit of the response slot.

公开(公告)号：US20250021129A1

公开(公告)日：2025-01-16

申请号：US18897011

申请日：2024-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanwoo NOH ,  Sungho SEO ,  Yongwoo JEONG ,  Dongwoo NAM ,  Myungsub SHIN ,  Hyunkyu JANG

IPC: G06F1/08 ,  G06F1/04 ,  G06F3/06 ,  G06F13/42 ,  G11C7/22 ,  G11C16/32 ,  H04L7/00

Abstract: A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

公开(公告)号：US20240370196A1

公开(公告)日：2024-11-07

申请号：US18380945

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Youngmin LEE ,  Seongheum BAIK ,  Myungsub SHIN ,  Seongyong JANG ,  Gyuseok CHOE

IPC: G06F3/06

Abstract: Disclosed is a storage device which includes a nonvolatile memory device that includes a plurality of erase units each including a plurality of memory cells, and a memory controller. Based on an open zone request received from an external host device, the memory controller allocates a zone to at least one erase unit among the plurality of erase units and permits only a sequential write with respect to the zone. The memory controller generates a map table mapping sequential logical addresses of data written in the zone to sequential physical addresses. Based on a partial invalidation request received from the external host device, the memory controller manages data corresponding to the partial invalidation request from among the data written in the zone as invalid data while maintaining the map table.

公开(公告)号：US20240272816A1

公开(公告)日：2024-08-15

申请号：US18497087

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseok CHOE ,  Seongheum BAIK ,  Myungsub SHIN ,  Youngmin LEE ,  Seongyong JANG

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0679

Abstract: A storage device and an operating method of the same are disclosed. The storage device includes a memory controller and a non-volatile memory, wherein the memory controller is configured to calculate a number of zones, which are spaces allocated to logical addresses, based on a cell area size of first storage areas of the non-volatile memory, and provide the number of zones to a host, is configured to generate multiple zones of a number within the calculated number of zones, and to map a logical address of each zone to a physical address of at least one of the first storage areas, and is configured to, in response to a first write request from the host, write data included in the first write request into first storage areas corresponding to a zone indicated by the first write request.

公开(公告)号：US20220066689A1

公开(公告)日：2022-03-03

申请号：US17238680

申请日：2021-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haesung JUNG ,  Sungho SEO ,  Myungsub SHIN ,  Seongyong JANG

IPC: G06F3/06

Abstract: Provided are a storage device configured to perform high-speed link startup and a storage system including the storage device. The storage system performs data communication through a connected transmission lane and a connected reception lane from among a plurality of lanes between a host and the storage device. The host transmits an activate period of the connected transmission lane, which is less than a first time period, to the connected reception lane, and the storage device receives the activate period of the connected reception lane, which is less than the first time period. The host and the storage device perform link startup in a high-speed mode through the connected transmission lane and the connected reception lane, based on the activate period being less than the first time period.