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    UNIVERSAL SERIAL BUS COMMUNICATIONS SYSTEM
    1.
    发明申请
    UNIVERSAL SERIAL BUS COMMUNICATIONS SYSTEM 审中-公开

    公开(公告)号：US20180052800A1

    公开(公告)日：2018-02-22

    申请号：US15463009

    申请日：2017-03-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Cheon-Su LEE ,  Rohitaswa BHATTACHARYA

    IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

    CPC classification number: G06F13/4282 ,  G06F13/36 ,  G06F13/4068 ,  G06F2213/0042

    Abstract: A universal serial bus (USB) communication system includes a USB host that divides one data stream into first through (n)th sub-data streams and transmits the first through (n)th sub-data streams via first through (n)th USB host channels, respectively, a USB device that receives the first through (n)th sub-data streams via first through (n)th USB device channels, respectively and restores the data stream by combining the first through (n)th sub-data streams, and first through (n)th cables that are connected to the first through (n)th USB host channels via first through (n)th USB host ports and connected to the first through (n)th USB device channels via first through (n)th USB device ports. Here, the first through (n)th cables connect the first through (n)th USB host channels to the first through (n)th USB device channels, respectively.

    ELECTRONIC SYSTEMS, FAULT DETECTING METHODS THEREOF, SYSTEM ON CHIPS, AND BUS SYSTEMS
    6.
    发明申请
    ELECTRONIC SYSTEMS, FAULT DETECTING METHODS THEREOF, SYSTEM ON CHIPS, AND BUS SYSTEMS 有权

    公开(公告)号：US20220093470A1

    公开(公告)日：2022-03-24

    申请号：US17536580

    申请日：2021-11-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Cheonsu LEE ,  Rohitaswa BHATTACHARYA

    IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

    Abstract: An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path.

    ELECTRONIC SYSTEMS, FAULT DETECTING METHODS THEREOF, SYSTEM ON CHIPS, AND BUS SYSTEMS
    7.
    发明申请
    ELECTRONIC SYSTEMS, FAULT DETECTING METHODS THEREOF, SYSTEM ON CHIPS, AND BUS SYSTEMS 有权

    公开(公告)号：US20210149765A1

    公开(公告)日：2021-05-20

    申请号：US16939310

    申请日：2020-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Cheonsu LEE ,  Rohitaswa BHATTACHARYA

    IPC: G06F11/10 ,  G06F13/16

    Abstract: An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path.

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