公开(公告)号：US09905288B2

公开(公告)日：2018-02-27

申请号：US15435383

申请日：2017-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Woo Ryu ,  Sang-Kyu Kang

IPC: G11C8/00 ,  G11C11/4096 ,  G11C11/4076 ,  G11C8/18 ,  G06F1/12 ,  G06F1/08

CPC classification number: G11C11/4096 ,  G06F1/08 ,  G06F1/12 ,  G11C7/1003 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4076 ,  G11C17/16 ,  G11C29/023 ,  G11C2029/0411

Abstract: A semiconductor memory device includes a memory cell array and a control logic circuit. The control logic circuit controls access to the memory cell array based on a command and an address. The semiconductor memory device performs a write operation to write data in the memory cell array and performs a read operation to read data from the memory cell array in synchronization with a clock signal from an external memory controller. The semiconductor memory device performs the write operation and the read operation in different data strobe modes in which the semiconductor memory device uses different numbers of data strobe signals according to a frequency of the clock signal.

公开(公告)号：US10559550B2

公开(公告)日：2020-02-11

申请号：US16055199

申请日：2018-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungbae Lee ,  Kwanghyun Kim ,  Sang-Kyu Kang ,  Do Kyun Kim ,  DongMin Kim ,  Ji Hyun Ahn

IPC: G11C5/04 ,  H01L25/065 ,  G11C11/4076 ,  H01L23/538 ,  H01L27/108 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/406

Abstract: A memory device includes a first volatile memory chip that includes a first volatile memory cell array storing first data and that receives or outputs the first data at a first bandwidth, and a second volatile memory chip that includes a second volatile memory cell array storing second data and that receives or outputs the second data at a second bandwidth different from the first bandwidth.

公开(公告)号：US10186304B2

公开(公告)日：2019-01-22

申请号：US15692132

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kyu Kang

IPC: G11C7/22 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0891 ,  G11C5/04 ,  G11C7/02 ,  G11C7/10 ,  H01L25/10

Abstract: A memory device includes a first data buffer receiving data of a first frequency band or a second frequency band, a first clock buffer providing a clock signal of the first frequency band to the first data buffer when the first data buffer receives the data of the first frequency band and providing a clock signal of the second frequency band to the first data buffer when the first data buffer receives the data of the second frequency band, a second data buffer receiving the data of the first frequency band or the second frequency band and receiving the clock signal of the second frequency band from the first clock buffer in response to receiving the data of the second frequency band, and a second clock buffer providing the clock signal of the first frequency band to the second data buffer in a first frequency band operation.

公开(公告)号：US10109344B2

公开(公告)日：2018-10-23

申请号：US15389539

申请日：2016-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Kyu Kang

IPC: G11C11/4096 ,  G11C5/02 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4094 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4091

Abstract: A semiconductor memory device includes a memory cell array including a plurality of bank arrays and a control logic circuit. The control logic circuit controls access to the memory cell array in response to a command and an address. A first number of memory cells are coupled to a bit-line of a first bank array of the plurality of bank arrays, a second number of memory cells are coupled to a bit-line of a second bank array of the plurality of bank arrays and the first number is different from the second number.

公开(公告)号：US09620193B2

公开(公告)日：2017-04-11

申请号：US14793749

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hee Hwang ,  Sang-Kyu Kang ,  Dong-Yang Lee ,  Jae-Yeon Choi ,  Jong-Hyun Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/40611 ,  G11C7/1063 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.