公开(公告)号：US20170077102A1

公开(公告)日：2017-03-16

申请号：US15083819

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/45 ,  H01L23/522

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10876

Abstract: A semiconductor device includes storage electrodes on a substrate and one or more supporters configured to couple one or more portions of the storage electrodes. The semiconductor device may include multiple non-intersecting supporters extending in parallel to a surface of the substrate. At least one supporter may have an upper surface that is substantially coplanar with upper surfaces of the storage electrodes. The storage electrodes may include a capacitor dielectric layer that conformally covers one or more surfaces of the storage electrodes and one or more supporters. A storage electrode may include upper and lower storage electrodes coupled together. The upper and lower storage electrodes may have different horizontal widths.

Abstract translation: 半导体器件包括衬底上的存储电极和被配置为耦合存储电极的一个或多个部分的一个或多个支撑器。 半导体器件可以包括平行于衬底的表面延伸的多个不相交的支撑体。 至少一个支撑件可以具有与存储电极的上表面基本上共面的上表面。 存储电极可以包括保形地覆盖存储电极的一个或多个表面和一个或多个支持者的电容器电介质层。 存储电极可以包括耦合在一起的上部和下部存储电极。 上下存储电极可以具有不同的水平宽度。

公开(公告)号：US20180301459A1

公开(公告)日：2018-10-18

申请号：US15952350

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Daeik KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Semyeong JANG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02 ,  B08B7/00

Abstract: A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.

公开(公告)号：US20170170185A1

公开(公告)日：2017-06-15

申请号：US15262025

申请日：2016-09-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-Eun KIM ,  Yong Kwan KIM ,  Sehyoung AHN ,  Semyeong JANG ,  Jaehyoung CHOI ,  Bong-Soo KIM ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L21/283 ,  H01L21/3115 ,  H01L49/02

CPC classification number: H01L27/1085 ,  H01L21/283 ,  H01L21/31155 ,  H01L28/00 ,  H01L28/60

Abstract: A method of fabricating a semiconductor device includes forming a mold structure including a lower support layer and an upper support layer sequentially stacked on a substrate, doping portions of the upper and lower support layers with impurities to divide each of the upper and lower support layers into first portions doped with the impurities and a second portion surrounding the first portions in a plan view, and removing the first portions of the upper and lower support layers to form an upper support pattern having first openings and a lower support pattern having second openings.

公开(公告)号：US20170062347A1

公开(公告)日：2017-03-02

申请号：US15095327

申请日：2016-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun KIM ,  Yongkwan KIM ,  Semyeong JANG ,  Jaehyoung CHOI ,  Yoosang HWANG ,  Bong-Soo KIM

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108

CPC classification number: H01L23/4821 ,  H01L21/76264 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L29/0649

Abstract: A semiconductor device includes first and second bit line structures on a substrate and spaced apart from each other, a via plug partially filling between the first and second bit line structures, a via pad in contact with an upper surface of the via plug and an upper sidewall of the first bit line structure, the via pad being spaced apart from an upper portion of the second bit line structure, a first cavity filled with air being between the via plug and the first bit line structure and a second cavity filled with air between the via plug and the second bit line structure, A gap capping spacer having a first portion on the upper sidewall of the first bit line structure and a second portion covers the first air spacer. A horizontal width of the first portion is smaller than that of the second portion.

Abstract translation: 半导体器件包括在衬底上彼此间隔开的第一和第二位线结构，部分地填充在第一和第二位线结构之间的通孔插头，与通孔插头的上表面接触的通孔焊盘和上部 第一位线结构的侧壁，通孔焊盘与第二位线结构的上部间隔开，填充有通孔插塞和第一位线结构之间的空气的第一腔体和填充有空气的第二腔体， 所述通孔插头和所述第二位线结构。具有位于所述第一位线结构的上侧壁上的第一部分的间隙封盖间隔件以及覆盖所述第一空气间隔件的第二部分。 第一部分的水平宽度小于第二部分的水平宽度。

公开(公告)号：US20150340284A1

公开(公告)日：2015-11-26

申请号：US14569980

申请日：2014-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung KIM ,  Yong Kwan KIM ,  Jemin PARK ,  Semyeong JANG ,  Sangyeon HAN ,  Yoosang HWANG

IPC: H01L21/768 ,  H01L29/66

CPC classification number: H01L27/1288 ,  H01L21/7688 ,  H01L27/10814 ,  H01L27/10891

Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.

Abstract translation: 本发明构思提供了制造半导体器件的方法。 该方法可以包括提供衬底，在衬底上堆叠导电层和下掩模层，在下掩模层上形成各自具有岛状的多个硬掩模层，形成具有岛形的多个上掩模图案，其布置成 暴露下掩模层的部分，蚀刻下掩模层的暴露部分以暴露导电层的部分，并且蚀刻导电层的暴露部分以形成多个接触孔，每个接触孔暴露衬底的一部分。