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公开(公告)号：US20240194595A1
公开(公告)日：2024-06-13
申请号：US18382661
申请日：2023-10-23
发明人： Eunjung KIM
IPC分类号： H01L23/528 , H01L23/522 , H10B12/00
CPC分类号： H01L23/5283 , H01L23/5226 , H10B12/0335 , H10B12/482 , H10B12/485
摘要： A semiconductor device includes a wiring line on a substrate, a first line portion having a line shape in a first direction, a head hammer pattern connected to an end of the first line portion in the first direction; a second wiring line spaced from the first wiring line in a second direction perpendicular to the first direction, the second wiring line including a second line portion parallel to the first line portion; a first contact plug electrically connecting the first line portion and the second line portion, the first contact plug being positioned adjacent to the first end of the first line portion and a second end of the second line portion in the first direction. The first contact plug has a bottom surface higher than a bottom surface of the first and second wiring lines. The upper surface of the first head hammer pattern contacts an insulation material.
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公开(公告)号：US20240074146A1
公开(公告)日：2024-02-29
申请号：US18116475
申请日：2023-03-02
发明人： Eunjung KIM , Eun A KIM
CPC分类号： H10B12/315 , H10B12/0335 , H10B61/22 , H10B63/10 , H10B63/30
摘要： A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device includes an active pattern; a gate structure on the active pattern; a bit-line structure electrically connected to the active pattern; a storage node contact electrically connected to the active pattern; and a landing pad electrically connected to the storage node contact, wherein the landing pad includes a first pad flat sidewall and a second pad flat sidewall that are opposite to each other, a third pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a fourth pad flat sidewall between the first pad flat sidewall and the second pad flat sidewall, a first pad curved sidewall between the first pad flat sidewall and the third pad flat sidewall, and a second pad curved sidewall between the first pad flat sidewall and the fourth pad flat sidewall.
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公开(公告)号：US20230004288A1
公开(公告)日：2023-01-05
申请号：US17858395
申请日：2022-07-06
发明人： Dongkyun KANG , Jaeho KO , Eunjung KIM , Hyeyoung MOON , Sungchan BAE , Eunhae LIM , Yookyung HAM
IPC分类号： G06F3/04886 , G06F3/0482
摘要： An electronic device includes a display; a memory configured to store at least one application and instructions, a processor configured to execute the instructions to execute at least one application, extract attribute information corresponding to at least one input field included in an execution screen of the at least one application in response to the execution of the at least one application, configure an input list based on the at least one input field, based on the extracted attribute information, configure a key input interface to correspond to the at least one input field, and control the display to at least partially display the execution screen of the at least one application, the input list, and the key input interface.
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公开(公告)号：US20240121947A1
公开(公告)日：2024-04-11
申请号：US18198980
申请日：2023-05-18
发明人： Eunjung KIM , Eun A KIM
IPC分类号： H10B12/00
CPC分类号： H10B12/482 , H10B12/485 , H10B12/488
摘要： A semiconductor device includes active patterns disposed on a substrate and including central portions, respectively, bit lines extending in a first direction on the central portions of the active patterns, word lines intersecting the active patterns in a second direction intersecting the first direction, fence patterns disposed between the bit lines adjacent to each other on the word lines, a contact trench region intersecting the active patterns and the word lines in a third direction intersecting the first and second directions, and bit line contacts and filling insulation patterns alternately arranged in the third direction in the contact trench region. The first to third directions are parallel to a bottom surface of the substrate. The filling insulation patterns are disposed between the word lines and the fence patterns, respectively.
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公开(公告)号：US20240298438A1
公开(公告)日：2024-09-05
申请号：US18503739
申请日：2023-11-07
发明人： Eunjung KIM
IPC分类号： H10B12/00
CPC分类号： H10B12/50 , H10B12/09 , H10B12/315
摘要： Disclosed are semiconductor devices and their fabrication methods. The semiconductor device may include a substrate including first and second cell active patterns and a dummy active pattern, a cell gate dielectric layer on the first and second cell active patterns and the dummy active pattern, a first cell gate conductive layer on the cell gate dielectric layer, and a bit-line structure connected to the first cell active pattern. A distance between the second cell and dummy active patterns is less than that between the first cell and dummy active patterns. The first cell gate conductive layer may include a dummy overlap section overlapping the dummy active pattern and the second cell active pattern, and a cell overlap section overlapping the first cell active pattern. A top surface of the dummy overlap section may be at a level higher than that of a top surface of the cell overlap section.
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公开(公告)号：US20220028868A1
公开(公告)日：2022-01-27
申请号：US17192069
申请日：2021-03-04
发明人： Hyewon KIM , Eunjung KIM , Geumjung SEONG , Jay-Bok CHOI
IPC分类号： H01L27/108 , H01L21/762
摘要： A semiconductor device includes a substrate including a cell region, a peripheral region, and a boundary region therebetween, a cell device isolation pattern on the cell region of the substrate to define cell active patterns, a peripheral device isolation pattern on the peripheral region of the substrate to define peripheral active patterns, and an insulating isolation pattern on the boundary region of the substrate, the insulating isolation pattern being between the cell active patterns and the peripheral active patterns, wherein a bottom surface of the insulating isolation pattern includes a first edge adjacent to a side surface of a corresponding one of the cell active patterns, and a second edge adjacent to a side surface of a corresponding one of the peripheral active patterns, the first edge being at a height lower than the second edge, when measured from a bottom surface of the substrate.
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公开(公告)号：US20180301459A1
公开(公告)日：2018-10-18
申请号：US15952350
申请日：2018-04-13
发明人： Eunjung KIM , Daeik KIM , Bong-Soo KIM , Jemin PARK , Semyeong JANG , Yoosang HWANG
IPC分类号： H01L27/108 , H01L21/768 , H01L21/02 , B08B7/00
摘要： A method of fabricating a semiconductor memory device includes forming a bit line and a bit line capping pattern on the semiconductor substrate, forming a first spacer covering a sidewall of the bit line capping pattern and a sidewall of the bit line, forming a contact plug in contact with a sidewall of the first spacer and having a top surface that is lower than an upper end of the first spacer, removing an upper portion of the first spacer, forming a first sacrificial layer closing at least an entrance of the void, forming a second spacer covering the sidewall of the bit line capping pattern and having a bottom surface in contact with a top surface of the first spacer, and removing the first sacrificial layer. The bit line capping pattern is on the bit line. The contact plug includes a void exposed on the top surface.
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8.发明申请公开(公告)号：US20180035388A1
公开(公告)日：2018-02-01
申请号：US15550188
申请日：2016-02-25
发明人： Hyochul KWAK , Eunjung KIM , Heewon KANG , Myungkwang BYUN
CPC分类号： H04W52/241 , H04W24/08 , H04W52/12 , H04W52/24 , H04W52/26 , H04W52/267 , H04W52/287 , H04W52/36 , H04W52/44 , H04W52/48 , H04W88/08
摘要： In order to solve a problem in which when a terminal is converted from an active state of transmitting data to an inactive state, the transmission power of the terminal rapidly increases, a base station can control the transmission power by predicting and reflecting, in a target SIR, a decrease in SIR which results from an increase in interference amount due to data transmission of another terminal. The present invention can ensure the quality of an uplink control channel by controlling power in consideration of the effect of interference, even when the terminal is in an inactive state.
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公开(公告)号：US20170236894A1
公开(公告)日：2017-08-17
申请号：US15383159
申请日：2016-12-19
发明人： Kyung-Eun Kim , Ki-hyung NAM , Byung Yoon KIM , Bong-Soo KIM , Eunjung KIM , Yoosang HWANG
IPC分类号： H01L49/02
CPC分类号： H01L28/56 , H01L27/10808 , H01L27/10817 , H01L27/10847 , H01L27/10852 , H01L28/75 , H01L28/82 , H01L28/88 , H01L28/90 , H01L28/92
摘要： Provided is a semiconductor device. The semiconductor device includes a capacitor structure including a plurality of lower electrodes, a dielectric layer that covers surfaces of the plurality of lower electrodes, and an upper electrode on the dielectric layer. The semiconductor device further includes a support structure that supports the plurality of lower electrodes. The support structure includes a first support region that covers sidewalls of one of the plurality of lower electrodes, and an opening that envelops the first support region when the semiconductor device is viewed in plan view.
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公开(公告)号：US20160034127A1
公开(公告)日：2016-02-04
申请号：US14803690
申请日：2015-07-20
发明人： Youbi SEO , Eunjung KIM , Yongman PARK , Hwayoun SUH , Eunhye JEE
IPC分类号： G06F3/0486 , G06F3/0484 , G06F3/0482
摘要： A method for displaying a user interface (UI) in an electronic device having a touch screen is provided. The method receiving an input for executing the UI of a first user function. The method further includes, in response to the input, displaying the UI having an object associated with the first user function and first items associated with the first user function and arranged in a radial pattern around the object, and when an item is selected from the first items and is dragged to the object, executing the first user function in connection with the particular item.
摘要翻译： 提供了一种在具有触摸屏的电子设备中显示用户界面（UI）的方法。 该方法接收用于执行第一用户功能的UI的输入。 所述方法还包括：响应于所述输入，显示具有与所述第一用户功能相关联的对象的UI和与所述第一用户功能相关联并且以所述对象周围的径向图案布置的第一项，以及当从所述第一用户功能中选择项目时 第一个项目并被拖动到对象，执行与特定项目相关的第一个用户功能。
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