公开(公告)号：US20220122651A1

公开(公告)日：2022-04-21

申请号：US17322065

申请日：2021-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjee KIM ,  Seungyeon KIM ,  Sangwan NAM ,  Hongsoo JEON ,  Jiho CHO

IPC: G11C11/4097 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4099 ,  G11C5/06

Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.

公开(公告)号：US20180248406A1

公开(公告)日：2018-08-30

申请号：US15757153

申请日：2016-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok BAE ,  Seungyeon KIM ,  Jongcheon WEE ,  Hwanseok CHOI ,  Jung-Su PARK ,  Kyunghwan LEE ,  Junhui LEE ,  Woojin JUNG ,  Chung-Hyo JUNG ,  Byoung-Uk YOON

IPC: H02J50/12 ,  H02J7/02 ,  G04G19/00 ,  H02J50/90 ,  H02J7/00

CPC classification number: H02J50/12 ,  G04G19/00 ,  H02J7/00 ,  H02J7/0044 ,  H02J7/02 ,  H02J7/025 ,  H02J50/90

Abstract: According to various embodiments, an electronic device configured to enable an external electronic device to be detachably mounted may include a housing, a power interface included in the housing and configured to be able to receive power from an external power source, a conductive pattern electrically coupled to the power interface and configured to be able to transmit power in a wirelessly fashion, and a plurality of members disposed around the conductive pattern and attracted by a magnet. Other various embodiments are also possible.

公开(公告)号：US20240081062A1

公开(公告)日：2024-03-07

申请号：US18143915

申请日：2023-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyeon KIM ,  Jiyoung KIM ,  In ho KANG ,  Woosung YANG ,  Jae-Eun LEE

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory includes a substrate that includes pass transistor regions, a peripheral circuit structure that includes pass transistors on the pass transistor regions, and a cell array structure on the peripheral circuit structure, the cell array structure including a plurality of cell array regions and a plurality of connection regions that are alternately arranged along a first direction. The cell array structure includes a stack structure including conductive patterns vertically stacked and correspondingly connected to the pass transistors. The stack structure includes stepwise structures on the connection regions. The connection regions of the cell array structure correspondingly overlap the pass transistor regions of the peripheral circuit structure.