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公开(公告)号：US20220057968A1
公开(公告)日：2022-02-24
申请号：US17233816
申请日：2021-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wandong KIM , Jinyoung KIM , Sehwan PARK , Hyun Seo , Sangwan NAM
Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data, calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.
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公开(公告)号：US20240233824A1
公开(公告)日：2024-07-11
申请号：US18614908
申请日：2024-03-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myunghun LEE , Sangwan NAM , Taemin OK
IPC: G11C16/04 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/40 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/40 , H10B43/50
CPC classification number: G11C16/0483 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/40 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/40 , H10B43/50
Abstract: An integrated circuit device includes a peripheral circuit structure including a lower substrate, an arc protection diode in the lower substrate, and a common source line driver connected to the arc protection diode, a conductive plate on the peripheral circuit structure, a cell array structure overlapping the peripheral circuit structure in a vertical direction with the conductive plate therebetween, and a first wiring structure connected between the arc protection diode and the conductive plate.
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3.发明公开公开(公告)号：US20240029814A1
公开(公告)日：2024-01-25
申请号：US18374026
申请日：2023-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung KIM , Ilhan PARK , Kyoman KANG , Sangwan NAM
CPC classification number: G11C29/50004 , G11C7/1039 , G11C7/1045 , G11C7/1057 , G11C7/1084 , G11C8/18 , G11C16/28 , G11C29/44 , G11C2029/1202
Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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公开(公告)号：US20230121078A1
公开(公告)日：2023-04-20
申请号：US17954663
申请日：2022-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Bongkil JUNG , Sangwan NAM , Keeho JUNG
Abstract: Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.
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公开(公告)号：US20220277801A1
公开(公告)日：2022-09-01
申请号：US17749607
申请日：2022-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung KIM , Ilhan PARK , Kyoman KANG , Sangwan NAM
Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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Patent Agency Ranking
公开(公告)号：US20220130474A1
公开(公告)日：2022-04-28
申请号：US17334045
申请日：2021-05-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yonghyuk CHOI , Sangwan NAM , Jaeduk YU , Yohan LEE
Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.
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公开(公告)号：US20220122651A1
公开(公告)日：2022-04-21
申请号：US17322065
申请日：2021-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yoonjee KIM , Seungyeon KIM , Sangwan NAM , Hongsoo JEON , Jiho CHO
IPC: G11C11/4097 , G11C11/408 , G11C11/4093 , G11C11/4099 , G11C5/06
Abstract: A memory device includes a peripheral circuit area including a first substrate and circuit elements on the first substrate, at least a portion of the circuit elements providing a source driver, and a cell area including a second substrate stacked with the peripheral circuit area in a first direction, perpendicular to an upper surface of the first substrate, and cell blocks and dummy blocks arranged in a second direction, parallel to an upper surface of the second substrate. Each of the cell blocks includes gate electrode layers and insulating layers alternately stacked on the second substrate, and channel structures extending in the first direction to penetrate through the gate electrode layers and the insulating layers and to be connected to the second substrate, at least one source contact block, among the dummy blocks, includes a first dummy insulating region on the second substrate, and source contacts extending in the first direction, penetrating through the first dummy insulating region and connected to the second substrate, and the source contacts are connected to the source driver through metal wirings in an upper portion of the cell area.
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公开(公告)号：US20210343342A1
公开(公告)日：2021-11-04
申请号：US17096245
申请日：2020-11-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Myunghun Lee , Sangwan NAM , Taemin OK
IPC: G11C16/04 , G11C16/26 , H01L23/528
Abstract: An integrated circuit device includes a peripheral circuit structure including a lower substrate, an arc protection diode in the lower substrate, and a common source line driver connected to the arc protection diode, a conductive plate on the peripheral circuit structure, a cell array structure overlapping the peripheral circuit structure in a vertical direction with the conductive plate therebetween, and a first wiring structure connected between the arc protection diode and the conductive plate.
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公开(公告)号：US20210034295A1
公开(公告)日：2021-02-04
申请号：US16807405
申请日：2020-03-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jiyeon SHIN , Sangwan NAM , Sangwon PARK
IPC: G06F3/06
Abstract: A method includes performing a first sensing operation to sense write setting data stored in first memory cells of a first memory plane and store first read setting data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense the write setting data stored in second memory cells of a second memory plane and store second read setting data in a second page buffer circuit of the second memory plane and performing a dump-down operation to store restored setting data corresponding to the write setting data in a buffer based on the first read setting data and the second read setting data.
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公开(公告)号：US20230044730A1
公开(公告)日：2023-02-09
申请号：US17968912
申请日：2022-10-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wandong KIM , Jinyoung KIM , Sehwan PARK , Hyun Seo , Sangwan NAM
Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data; calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.
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