公开(公告)号：US20230197604A1

公开(公告)日：2023-06-22

申请号：US17845209

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： John Soo KIM ,  Min Wook CHUNG ,  Kyoung Suk KIM ,  Soo Kyung KIM ,  Won Suk LEE ,  Jong Jin LEE

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76846 ,  H01L21/76877

Abstract: A semiconductor device is provided. The semiconductor device includes: a first interlayer insulating film defining a lower wiring trench; a lower wiring structure including a first lower barrier film which extends along sidewalls of the lower wiring trench, and a lower filling film which is on the first lower barrier film; a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film defining an upper wiring trench which exposes at least part of the lower wiring structure; and an upper wiring structure provided in the upper wiring trench and connected to the lower wiring structure. An upper surface of the first lower barrier film is closer to a bottom surface of the lower wiring trench than each of an upper surface of the first interlayer insulating film and an upper surface the lower filling film. The upper surface of the first lower barrier film is concave.

公开(公告)号：US20240313066A1

公开(公告)日：2024-09-19

申请号：US18409031

申请日：2024-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo Kyung KIM ,  Chan HWANG ,  Jonghyun JUNG ,  Moosong LEE

IPC: H01L29/40 ,  G03F7/00 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L29/401 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/32139 ,  G03F7/2004 ,  G03F7/2022 ,  G03F7/7045

Abstract: A method of fabricating a semiconductor device may include providing a substrate including cell and peripheral regions, forming a cell gate structure on the cell region, forming a peripheral gate structure on the peripheral region, forming a bit line structure on the cell region, forming a preliminary conductive layer to cover the bit line structure and the peripheral gate structure, and etching the preliminary conductive layer to form a landing pad and peripheral conductive pads. The etching of the preliminary conductive layer may include forming lower and photoresist layers on the preliminary conductive layer, performing a first exposure process on the photoresist layer, performing a second exposure process on the photoresist layer, and etching the preliminary conductive layer using the photoresist and lower layers as an etch mask. The first exposure process may expose a portion of the photoresist layer that is on the cell region to light.

公开(公告)号：US20220091497A1

公开(公告)日：2022-03-24

申请号：US17407425

申请日：2021-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Ho YUN ,  Soo Kyung KIM ,  Jaikyun PARK ,  Donghoon LEE ,  Rankyung JUNG ,  Soonmok HA

IPC: G03F1/24 ,  H01L21/027

Abstract: A reflective mask includes a central region and first and second peripheral regions at opposite sides of the central region, respectively, the first peripheral region including a first out-of-band region having a first edge region extending in a first direction, and a first expansion region between the first edge region and the central region, and a first outer auxiliary region adjacent to the first expansion region of the first out-of-band region in the first direction, the first outer auxiliary region having a first auxiliary pattern region.