公开(公告)号：US09070677B2

公开(公告)日：2015-06-30

申请号：US14171059

申请日：2014-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojeoung Park

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L23/552 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip on the lower substrate, a lower graphene layer on the lower semiconductor chip, and a lower molding layer between the lower substrate and the lower graphene layer. An upper package is on the lower substrate, the upper package spaced apart from the lower package, the upper package comprising an upper substrate, an upper semiconductor chip, and an upper molding layer. Lower conductive bumps are positioned between the lower substrate and the upper substrate, the lower bumps comprising a ground bump and a signal transmitting bump.

Abstract translation: 半导体封装包括下封装，其包括下基板，下基板上的下半导体芯片，下半导体芯片上的下石墨烯层，以及下基板和下石墨烯层之间的下模制层。 上封装在下基板上，上封装与下封装间隔开，上封装包括上基板，上半导体芯片和上模制层。 下导电凸块位于下基板和上基板之间，下凸块包括接地凸块和信号传输凸块。

公开(公告)号：US20230113465A1

公开(公告)日：2023-04-13

申请号：US17854659

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minki Kim ,  Seungduk Baek ,  Soojeoung Park ,  Hyuekjae Lee

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

公开(公告)号：US10163838B2

公开(公告)日：2018-12-25

申请号：US15499272

申请日：2017-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojeoung Park ,  Bona Baek ,  Yongho Kim

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor chip, pads provided on the semiconductor chip, and insulating patterns provided on the semiconductor chip. The insulating patterns having openings exposing the pads, and conductive patterns are provided in the openings and coupled to the pads. When viewed in a plan view, two opposite ends of the pads are spaced apart from the conductive patterns and two opposite ends of the conductive patterns are spaced apart from the pads. Additionally, when viewed in a plan view, the conductive patterns include a first conductive pattern whose length is parallel to a first direction and a second conductive pattern whose length is parallel to a second direction. The first and second directions are oblique to each other.