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    Semiconductor device including interlayer support patterns on a substrate
    1.
    发明授权
    Semiconductor device including interlayer support patterns on a substrate 有权

    公开(公告)号：US10115734B2

    公开(公告)日：2018-10-30

    申请号：US15398735

    申请日：2017-01-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang Gn Yun ,  Sun Young Kim

    IPC: H01L29/792 ,  H01L27/11582 ,  H01L23/528

    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes interlayer support patterns sequentially stacked on a substrate, horizontal conductive patterns sequentially stacked on the substrate, and an interlayer insulating layer disposed between the interlayer support patterns, extending between the horizontal conductive patterns, and disposed in parallel with a surface of the substrate. The interlayer insulating layer is in contact with the interlayer support patterns. A conductive structure extends in a direction perpendicular to the substrate. Vertical structures extending through the horizontal conductive patterns and the interlayer insulating layer are formed.

    Connection member and electronic device including the same
    6.
    发明授权
    Connection member and electronic device including the same 有权

    公开(公告)号：US10608314B2

    公开(公告)日：2020-03-31

    申请号：US15454537

    申请日：2017-03-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung Won Park ,  Sun Young Kim ,  Seung Yup Lee

    IPC: H01Q1/12 ,  H05K7/14 ,  H01Q1/50

    Abstract: An electronic device is provided. The electronic device includes a circuit board, a first conductive member electrically connected to the circuit board at a first point, a second conductive member electrically connected to the circuit board at a second point, and a connection member connecting the first conductive member and the second conductive member, where the connection member includes a first conductive layer electrically connected to the first conductive member, a second conductive layer electrically connected to the second conductive member, and a dielectric layer disposed between the first conductive layer and the second conductive layer.

    Memory device
    7.
    发明授权
    Memory device 有权

    公开(公告)号：US10446580B2

    公开(公告)日：2019-10-15

    申请号：US16298349

    申请日：2019-03-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jang Gn Yun ,  Sun Young Kim ,  Hoo Sung Cho

    IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/522

    Abstract: A memory device includes a pair of common source lines disposed on a substrate spaced apart from each other and extended in a first direction; a plurality of ground select lines disposed between the pair of common source lines, extended in the first direction, and disposed on the same level; a plurality of word lines disposed on the plurality of ground select lines between the pair of common source lines, extended in the first direction, and disposed on the same level, at least a portion of the plurality of word lines being connected by a connection electrode; and a plurality of first separation insulating patterns disposed between individual ground select lines of a portion of the plurality of ground select lines and extended in the first direction. The at least portion of the plurality of word lines is connected by a connection electrode.

    Memory device
    8.
    发明授权
    Memory device 有权

    公开(公告)号：US11950420B2

    公开(公告)日：2024-04-02

    申请号：US17517220

    申请日：2021-11-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Su Jin Park ,  Sun Young Kim ,  Jang Gn Yun

    IPC: H10B43/27 ,  H01L23/528 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/50

    CPC classification number: H10B43/27 ,  H01L23/528 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/50

    Abstract: A memory device includes gate electrode layers stacked on an upper surface of a substrate and each including a plurality of unit electrodes extending in a first direction, and a plurality of connecting electrodes connecting the unit electrodes to each other. The memory device also includes channel structures extending through the gate electrode layers in a direction perpendicular to the upper surface of the substrate, first common source lines extending in the first direction and interposed between the unit electrodes, and second common source lines extending in the first direction between the first common source lines and each having a first line and a second line separated from each other in the first direction by the connecting electrodes.

    MEMORY DEVICES HAVING SENSE AMPLIFIERS THEREIN THAT SUPPORT OFFSET COMPENSATION AND METHODS OF OPERATING SAME
    9.
    发明公开
    MEMORY DEVICES HAVING SENSE AMPLIFIERS THEREIN THAT SUPPORT OFFSET COMPENSATION AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20240029782A1

    公开(公告)日：2024-01-25

    申请号：US18298999

    申请日：2023-04-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongil Lee ,  Younghun Seo ,  Sun Young Kim ,  Hoseok Lee

    IPC: G11C11/4091 ,  G11C11/4094

    CPC classification number: G11C11/4091 ,  G11C11/4094

    Abstract: A method of operating a bit line sense amplifier may include performing a normal precharge operation by charging a bit line, a complementary bit line, a sensing bit line, and a complementary sensing bit line to a precharge voltage, and then performing a first offset compensation operation by connecting the bit line to the sensing bit line, connecting the complementary bit line to the complementary sensing bit line, applying a first internal voltage greater than the precharge voltage to a P-type sense amplifier, and applying a second internal voltage less than the precharge voltage to an N-type sense amplifier. A second offset compensation operation is performed by applying the precharge voltage to the P-type sense amplifier concurrently with applying the second internal voltage to the N-type sense amplifier. A bit line offset detection operation is performed by separating the bit line from the sensing bit line, separating the complementary bit line from the complementary sensing bit line, connecting the sensing bit line to the complementary sensing bit line, and applying the precharge voltage to the N-type sense amplifier.

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