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    Memory systems and devices that support clock-to-clock alignment, training and methods of operating same
    5.
    发明授权
    Memory systems and devices that support clock-to-clock alignment, training and methods of operating same 有权

    公开(公告)号：US10593382B2

    公开(公告)日：2020-03-17

    申请号：US16045887

    申请日：2018-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Seok Kang ,  Byung-Chul Kim

    IPC: G11C7/22 ,  G06F3/06 ,  G11C7/10 ,  H03L7/00

    Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training. A first loop operation includes: receiving first phase control information, which is generated based on the division ratio information, from the memory controller, dividing the data clock signal based on the division ratio to generate a division data clock signal, selecting a first phase from among a plurality of phases based on the first phase control information, generating a first comparison target clock signal that is shifted from the division data clock signal by the first phase, comparing a phase of the first comparison target clock signal with a phase of the main clock signal, and transmitting a first phase comparison result to the memory controller.

    Semiconductor memory device having resistive memory cells and method of testing the same
    6.
    发明授权
    Semiconductor memory device having resistive memory cells and method of testing the same 有权
    具有电阻式存储单元的半导体存储器件及其测试方法

    公开(公告)号：US09147500B2

    公开(公告)日：2015-09-29

    申请号：US13945007

    申请日：2013-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye-Jin Kim ,  Hyung-Rok Oh ,  Dong-Seok Kang ,  Dong-Hyun Sohn ,  Sang-Beom Kang ,  Chul-Woo Park ,  Yun-Sang Lee

    IPC: G11C11/00 ,  G11C29/10 ,  G11C11/16 ,  G11C29/32 ,  G11C29/34 ,  G11C29/26

    CPC classification number: G11C29/10 ,  G11C11/16 ,  G11C11/161 ,  G11C11/165 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/32 ,  G11C29/34 ,  G11C2029/2602

    Abstract: A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.

    Abstract translation: 半导体存储器件包括存储单元阵列，模式寄存器组和测试电路。 存储单元阵列包括多个字线，多个位线和多个自旋转移转矩磁阻随机存取存储器（STT-MRAM）单元，每个STT-MRAM单元设置在每个字线的交叉区域 和位线，并且STT-MRAM单元包括磁隧道结（MTJ）元件和单元晶体管。 单元晶体管的栅极耦合到字线，单元晶体管的第一电极通过MTJ元件耦合到位线，并且单元晶体管的第二电极耦合到源极线。 模式寄存器组被配置为设置测试模式，并且测试电路被配置为通过使用模式寄存器集执行测试操作。

    MEMORY DEVICE AND DIVIDED CLOCK CORRECTION METHOD THEREOF
    8.
    发明申请
    MEMORY DEVICE AND DIVIDED CLOCK CORRECTION METHOD THEREOF 审中-公开

    公开(公告)号：US20200013441A1

    公开(公告)日：2020-01-09

    申请号：US16571868

    申请日：2019-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Seok Kang ,  SEUNGJUN BAE

    IPC: G11C7/10 ,  H04L25/02 ,  H04L7/08 ,  H04L7/00 ,  H03L7/085 ,  G11C7/22

    Abstract: A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.

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