公开(公告)号：US20140248755A1

公开(公告)日：2014-09-04

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将绝缘层保持在有源区域之间的沟槽中 在第二设备区域中。 还讨论了相关的方法和设备。

公开(公告)号：US09425208B2

公开(公告)日：2016-08-23

申请号：US14682567

申请日：2015-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Soo Kim ,  Sung-Hoi Hur ,  So-Wi Chin

IPC: H01L29/66 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42356 ,  H01L29/78 ,  H01L29/7827

Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.

Abstract translation: 一种垂直存储装置，包括：包括单元区域和外围电路区域的基板，所述外围电路区域包括栅极结构，所述栅极结构包括晶体管，所述单元区域上的多个沟道，每个所述沟道沿垂直于第一方向延伸 相对于衬底的顶表面，沿着第一方向堆叠并且彼此间隔开的多个栅极线，围绕沟道的外侧壁的栅极线以及电池区域和外围电路区域之间的阻挡结构 ，其中所述阻挡结构的高度大于所述外围区域中的所述栅极结构的高度。

公开(公告)号：US08952438B2

公开(公告)日：2015-02-10

申请号：US13901205

申请日：2013-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

Abstract translation: 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。

公开(公告)号：US08951881B2

公开(公告)日：2015-02-10

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区 在第二设备区域中。 还讨论了相关的方法和设备。

公开(公告)号：US20130256775A1

公开(公告)日：2013-10-03

申请号：US13901205

申请日：2013-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-il Shim ,  Sung-Hoi Hur ,  Jin-Ho Kim ,  Su-Youn Yi

IPC: H01L27/115

CPC classification number: H01L27/1158 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described.

Abstract translation: 垂直NAND闪速存储器件包括在衬底上具有面和串联的闪存单元串的衬底。 第一闪存单元与面相邻，并且最后的闪存单元远离面。 闪存单元包括堆叠在表面上的重复层图案和延伸穿过一系列重复层图案的柱。 支柱包括至少一个斜壁。 串中重复层图案的系列中的至少两个具有不同的厚度。 还描述了其它垂直微电子器件和相关的制造方法。