公开(公告)号：US10559585B2

公开(公告)日：2020-02-11

申请号：US15871478

申请日：2018-01-15

申请人： Samsung Electronics Co., Ltd.

发明人： Kyoung-Hoon Kim ,  Hong-Soo Kim ,  Tae-Hee Lee

IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11556 ,  H01L23/522

摘要： A vertical memory device includes a conductive pattern structure on a first region of a substrate, the conductive pattern structure including a stack of interleaved conductive patterns and insulation layers. A pad structure is disposed on a second region of the substrate adjacent the first region of the substrate wherein edges of the conductive patterns are disposed at spaced apart points along a first direction to provide conductive pads arranged as respective steps in a staircase arrangement. A plurality of channel structures extends through the conductive pattern structure and a plurality of dummy channel structures extends through the pad structure. Respective contact plugs are disposed on the conductive pads. Numbers of the dummy channel structures per unit area passing through the conductive pads vary. Widths of the dummy channel structures passing through the conductive pads may also vary.

公开(公告)号：US10943922B2

公开(公告)日：2021-03-09

申请号：US16856611

申请日：2020-04-23

申请人： Samsung Electronics Co., Ltd.

发明人： Kyoung-Hoon Kim ,  Hong-Soo Kim ,  Ju-Yeon Lee

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L27/11556

摘要： A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.

公开(公告)号：US09425208B2

公开(公告)日：2016-08-23

申请号：US14682567

申请日：2015-04-09

申请人： Samsung Electronics Co., Ltd.

发明人： Hong-Soo Kim ,  Sung-Hoi Hur ,  So-Wi Chin

IPC分类号： H01L29/66 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42356 ,  H01L29/78 ,  H01L29/7827

摘要： A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.

摘要翻译： 一种垂直存储装置，包括：包括单元区域和外围电路区域的基板，所述外围电路区域包括栅极结构，所述栅极结构包括晶体管，所述单元区域上的多个沟道，每个所述沟道沿垂直于第一方向延伸 相对于衬底的顶表面，沿着第一方向堆叠并且彼此间隔开的多个栅极线，围绕沟道的外侧壁的栅极线以及电池区域和外围电路区域之间的阻挡结构 ，其中所述阻挡结构的高度大于所述外围区域中的所述栅极结构的高度。

公开(公告)号：US09165611B2

公开(公告)日：2015-10-20

申请号：US14157830

申请日：2014-01-17

申请人： Samsung Electronics Co., Ltd.

发明人： Jang-Gn Yun ,  Hong-Soo Kim ,  Hoo-Sung Cho

IPC分类号： H01L23/48 ,  G11C5/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/06

CPC分类号： G11C5/063 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

摘要翻译： 提供三维半导体器件的接线结构及其形成方法。 布线结构可以包括上字线和下字线，每个字线在纵向方向上延伸。 上字线可以包括在横向方向上仅延伸上部字线的一部分的凹部，下部字线可以包括由上部字线的凹部露出的布线区域。 布线结构还可以包括接触上部字线的上部接触插塞和与接线区域接触的下部接触插头。 上下接触塞可以在垂直方向上延伸。