公开(公告)号：US11626443B2

公开(公告)日：2023-04-11

申请号：US16926924

申请日：2020-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim

IPC: H01L21/00 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

公开(公告)号：US12166000B2

公开(公告)日：2024-12-10

申请号：US17541719

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Jungseob So ,  Taeseong Kim ,  Sohye Cho ,  Sonkwan Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: The semiconductor device includes a lower chip structure including a peripheral circuit, a first memory chip structure on the lower chip structure, and a second memory chip structure on the first memory chip structure. The first memory chip structure includes a first stack structure and a first vertical memory structure. The first stack structure includes first gate lines stacked in a vertical direction and extending in a first horizontal direction. The first vertical memory structure penetrates through the first gate lines in the vertical direction. The second memory chip structure includes a second stack structure and a second vertical memory structure. The second stack structure includes second gate lines stacked in the vertical direction and extending in a second horizontal direction, perpendicular to the first horizontal direction. The second vertical memory structure penetrates through the second gate lines in the vertical direction.

公开(公告)号：US12107109B2

公开(公告)日：2024-10-01

申请号：US18191218

申请日：2023-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L27/14634 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/1469 ,  H01L2224/08146 ,  H01L2224/80894

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

公开(公告)号：US11791211B2

公开(公告)日：2023-10-17

申请号：US17691178

申请日：2022-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L21/02068 ,  H01L21/76831

Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

公开(公告)号：US20210020543A1

公开(公告)日：2021-01-21

申请号：US16794782

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.

公开(公告)号：US20190386051A1

公开(公告)日：2019-12-19

申请号：US16233900

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yi Koan Hong ,  Taeseong Kim

IPC: H01L27/146 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

公开(公告)号：US11749586B2

公开(公告)日：2023-09-05

申请号：US17514218

申请日：2021-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sonkwan Hwang ,  Taeseong Kim ,  Hoonjoo Na ,  Kwangjin Moon ,  Hyungjun Jeon

IPC: H01L21/00 ,  H01L23/48 ,  H01L27/088 ,  H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L25/0657 ,  H01L27/0886 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit layer on the semiconductor substrate, first to nth metal wiring layers (where n is a positive integer) sequentially stacked on the semiconductor substrate and the integrated circuit layer, a first through via structure extending in a vertical direction toward the semiconductor substrate from a first via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate, and a second through via structure being apart from the first through via structure, extending in a vertical direction toward the semiconductor substrate from a second via connection metal wiring layer, which is one of the second to nth metal wiring layers other than the first metal wiring layer, and passing through the semiconductor substrate may be provided.

公开(公告)号：US11373932B2

公开(公告)日：2022-06-28

申请号：US16750579

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyoukyung Cho ,  Daesuk Lee ,  Jinnam Kim ,  Taeseong Kim ,  Kwangjin Moon ,  Hakseung Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L23/528 ,  H01L21/027 ,  H01L21/288 ,  H01L21/321

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first wiring layer, a first semiconductor substrate on the first wiring layer, a first dielectric layer on the first semiconductor substrate, a landing pad in the first wiring layer, a through hole that penetrates the first semiconductor substrate, the first dielectric layer, and the first wiring layer and exposes the landing pad, the through hole including a first hole and a second hole on a bottom end of the first hole, the second hole having a maximum diameter less than a minimum diameter of the first hole, and a mask layer on an upper lateral surface of the through hole.

公开(公告)号：US11133240B2

公开(公告)日：2021-09-28

申请号：US16794782

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Kwangjin Moon ,  Eunji Kim ,  Taeseong Kim ,  Sangjun Park

IPC: H01L23/48 ,  H01L25/18 ,  H01L21/768 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate including at least one semiconductor structure, an interlayer insulating layer disposed on the semiconductor substrate, at least one first via structure penetrating the semiconductor substrate and the interlayer insulating layer, including a first region having a first width at an upper surface of the interlayer insulating layer and a second region extending from the first region and having a second width at a lower surface of the semiconductor substrate, wherein a side surface of the first region and a side surface of the second region have different profiles at a boundary between the first region and the second region, and at least one second via structure penetrating the semiconductor substrate and the interlayer insulating layer and having a third width greater than the first width at an upper surface of the interlayer insulating layer.

公开(公告)号：US20210043575A1

公开(公告)日：2021-02-11

申请号：US16849085

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L23/538

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.