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    Wafer loaders having buffer zones
    1.
    发明授权
    Wafer loaders having buffer zones 有权
    具有缓冲区的晶片装载机

    公开(公告)号：US09502274B2

    公开(公告)日：2016-11-22

    申请号：US14281880

    申请日：2014-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Byung Lyul Park ,  Jumyong Park ,  Jisoon Park ,  Kyu-Ha Lee ,  Siyoung Choi

    IPC: H01L21/673

    CPC classification number: H01L21/6733 ,  H01L21/6732 ,  H01L21/67323 ,  H01L21/67326

    Abstract: Embodiments of the present inventive concepts provide a wafer loader having one or more buffer zones to prevent damage to a wafer loaded in the wafer loader. The wafer loader may include a plurality of loading sections that protrude from a main body and are configured to be arranged at various locations along an edge of the wafer. Each of the loading sections may include a groove into which the edge of the wafer may be inserted. The loading section may include first and second protrusions having first and second inner sides, respectively, that face each other to define the groove therebetween. At least one of the first and second inner sides may include a recess to define the buffer zone.

    Abstract translation: 本发明构思的实施例提供了具有一个或多个缓冲区的晶片装载器，以防止损坏装载在晶片装载器中的晶片。 晶片装载机可以包括从主体突出的多个装载部分，并被构造成沿着晶片的边缘布置在不同位置。 每个加载部分可以包括槽，其中可以插入晶片的边缘。 装载部分可以包括分别具有彼此面对以限定其间的凹槽的第一和第二内侧的第一和第二突起。 第一和第二内侧中的至少一个可以包括限定缓冲区的凹部。

    Semiconductor devices including through vias and methods of fabricating the same
    2.
    发明授权
    Semiconductor devices including through vias and methods of fabricating the same 有权

    公开(公告)号：US11295981B2

    公开(公告)日：2022-04-05

    申请号：US16734456

    申请日：2020-01-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Taeseong Kim ,  Kwangjin Moon

    IPC: H01L21/02 ,  H01L21/768

    Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

    Semiconductor device including through via, semiconductor package, and method of fabricating the same
    3.
    发明授权
    Semiconductor device including through via, semiconductor package, and method of fabricating the same 有权

    公开(公告)号：US10734430B2

    公开(公告)日：2020-08-04

    申请号：US16233900

    申请日：2018-12-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Taeseong Kim

    IPC: H01L23/48 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00

    Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

    Semiconductor device including through via, semiconductor package, and method of fabricating the same
    4.
    发明授权
    Semiconductor device including through via, semiconductor package, and method of fabricating the same 有权

    公开(公告)号：US11626443B2

    公开(公告)日：2023-04-11

    申请号：US16926924

    申请日：2020-07-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Taeseong Kim

    IPC: H01L21/00 ,  H01L27/146 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

    Semiconductor devices including through vias and methods of fabricating the same
    6.
    发明授权
    Semiconductor devices including through vias and methods of fabricating the same 有权

    公开(公告)号：US11791211B2

    公开(公告)日：2023-10-17

    申请号：US17691178

    申请日：2022-03-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Taeseong Kim ,  Kwangjin Moon

    IPC: H01L21/768 ,  H01L21/02

    CPC classification number: H01L21/76898 ,  H01L21/02068 ,  H01L21/76831

    Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.

    SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA, SEMICONDUCTOR PACKAGE, AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA, SEMICONDUCTOR PACKAGE, AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20190386051A1

    公开(公告)日：2019-12-19

    申请号：US16233900

    申请日：2018-12-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yi Koan Hong ,  Taeseong Kim

    IPC: H01L27/146 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

    Abstract: A semiconductor device including a first structure including a first conductive pattern, the first conductive pattern exposed on an upper portion of the first structure, a mold layer covering the first conductive pattern, a second structure on the mold layer, and a through via penetrating the second structure and the mold layer, the through via electrically connected to the first conductive pattern, the through via including a first via segment in the second structure and a second via segment in the mold layer, the second via segment connected to the first via segment, an upper portion of the second via segment having a first width and a middle portion of the second via segment having a second width greater than the first width may be provided.

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