公开(公告)号：US20230413424A1

公开(公告)日：2023-12-21

申请号：US18240619

申请日：2023-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop LEE ,  Hwanwook Park ,  Jeonghoon Baek ,  Dohyung Kim ,  Seunghee Mun ,  Dongyoon Seo ,  Jinoh Ahn

IPC: H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40 ,  G11C5/04

CPC classification number: H05K1/0246 ,  H01L25/112 ,  H01L25/0657 ,  H05K1/025 ,  G11C5/063 ,  G11C8/18 ,  G06F13/4086 ,  G11C5/04 ,  H05K2201/10159

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

公开(公告)号：US20220159827A1

公开(公告)日：2022-05-19

申请号：US17337850

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop LEE ,  Hwanwook PARK ,  Jeonghoon BAEK ,  Dohyung KIM ,  Seunghee MUN ,  Dongyoon SEO ,  Jinoh AHN

IPC: H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

公开(公告)号：US20220408550A1

公开(公告)日：2022-12-22

申请号：US17573156

申请日：2022-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongyoon SEO ,  Hwanwook PARK ,  Dohyung KIM ,  Bora KIM ,  Seungyeong LEE ,  Wonseop LEE ,  Yunho LEE ,  Yejin CHO

IPC: H05K1/02 ,  H05K1/11 ,  G11C11/4076

Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.

公开(公告)号：US20240431026A1

公开(公告)日：2024-12-26

申请号：US18749099

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeho CHOI ,  Jonghoon KIM ,  Dongyoon SEO ,  Dohyung KIM ,  Wonseop LEE ,  Daae HUH

IPC: H05K1/11 ,  H05K1/18

Abstract: An apparatus including via structures capable of reducing crosstalk effects is provided. The apparatus includes a printed circuit board (PCB) including sequentially stacked multi-layers, a first via structure that partially penetrates the multilayers of the PCB and is connected to a first metal plate on a first layer of the multilayers, and a second via structure adjacent to the first via structure in a horizontal direction, partially penetrating the multi-layers of the PCB, and connected to a second metal plate disposed on a second layer of the multi-layers. A portion where the first metal plate and the second metal plate overlap each other is configured to provide a first mutual capacitive coupling between the first and second via structures.

公开(公告)号：US20230013064A1

公开(公告)日：2023-01-19

申请号：US17947397

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop LEE ,  Hwanwook PARK ,  Jeonghoon BAEK ,  Dohyung KIM ,  Seunghee MUN ,  Dongyoon SEO ,  Jinoh AHN

IPC: H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40 ,  G11C5/04

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.