-
公开(公告)号:US12063736B2
公开(公告)日:2024-08-13
申请号:US18240619
申请日:2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseop Lee , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , G06F13/4086 , G11C5/04 , G11C5/063 , G11C8/18 , H01L25/0657 , H01L25/112 , H05K1/025 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
-
公开(公告)号:US11974391B2
公开(公告)日:2024-04-30
申请号:US17573156
申请日:2022-01-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Dongyoon Seo , Hwanwook Park , Dohyung Kim , Bora Kim , Seungyeong Lee , Wonseop Lee , Yunho Lee , Yejin Cho
IPC: H05K1/02 , G11C11/4076 , H05K1/11
CPC classification number: H05K1/0268 , G11C11/4076 , H05K1/11 , H05K1/116 , H05K2201/09445 , H05K2201/09481 , H05K2201/10159
Abstract: A PCB includes a plurality of layers spaced apart in a vertical direction, a first detection pattern and a second detection pattern and pads connected to the first detection pattern and the second detection pattern. The first detection pattern and the second detection pattern are provided in a respective one of a first layer and a second layer adjacent to each other such that the first detection pattern and the second detection pattern are opposed to each other. The pads are provided in an outmost layer. Each of the first detection pattern and the second detection includes at least one main segment extending in at least one of first and second horizontal directions and a diagonal direction. A time domain reflectometry connected to a pair of pads detects a misalignment of the PCB by measuring differential characteristic impedance of the first detection pattern and the second detection pattern.
-
3.
公开(公告)号:US20230422523A1
公开(公告)日:2023-12-28
申请号:US18180366
申请日:2023-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jiwon Kim , Dohyung Kim , Jiyoung Kim , Sukkang Sung
Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a stacked structure including gate electrodes extending in a first direction, a source structure on the stacked structure, and a second substrate in contact with the source structure. The source structure includes a first source conductive pattern between the second substrate and the stacked structure and a second source conductive pattern on the first source conductive pattern. The second source conductive pattern includes a first source part between the first source conductive pattern and the second substrate, a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part.
-
公开(公告)号:US20230413424A1
公开(公告)日:2023-12-21
申请号:US18240619
申请日:2023-08-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Wonseop LEE , Hwanwook Park , Jeonghoon Baek , Dohyung Kim , Seunghee Mun , Dongyoon Seo , Jinoh Ahn
CPC classification number: H05K1/0246 , H01L25/112 , H01L25/0657 , H05K1/025 , G11C5/063 , G11C8/18 , G06F13/4086 , G11C5/04 , H05K2201/10159
Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.
-
公开(公告)号:US11778719B2
公开(公告)日:2023-10-03
申请号:US16927050
申请日:2020-07-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dohyung Kim , Seongchul Hong , Kyungsik Kang , Insung Kim , Motoshi Sakai , Seulgi Lee , Jungchul Lee
CPC classification number: H05G2/008 , G02B19/0047 , G02B26/0816 , G02B26/0875 , H01S3/0071 , H01S3/2316
Abstract: A laser beam delivery apparatus of an extreme ultra violet light source may include a high power seed module configured to generate a laser beam, a power amplifier configured to amplify the laser beam generated by the high power seed module, a beam transfer module configured to collect and move the laser beam amplified by the power amplifier, a final focusing assembly optical platform configured to adjust focus of the laser beam collected and moved by the beam transfer module, and a focusing unit configured to focus the laser beam with the focus adjusted by the final focusing assembly optical platform to a target droplet. The power amplifier may include a position adjuster configured to adjust a position of the laser beam. The position adjuster may include a refraction plate having a flat surface. The power amplifier may include a pointing adjuster, which may include a mirror.
-
公开(公告)号:US20220147096A1
公开(公告)日:2022-05-12
申请号:US17470535
申请日:2021-09-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dohyung Kim , Minyoung Kang
Abstract: A system on chip includes: a functional circuit configured to perform a processing operation by receiving a supply voltage; a droop detection circuit configured to monitor the supply voltage and generate a detection signal indicating whether a droop of the supply voltage has occurred; a clock generation circuit configured to output a first clock signal having a first frequency; and a clock modulation circuit configured to receive the detection signal and the first clock signal, and provide a system clock signal to the functional circuit.
-
公开(公告)号:US11183148B2
公开(公告)日:2021-11-23
申请号:US16662290
申请日:2019-10-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Yongmin Tai , Dohyung Kim , Jinsung Kang , Kyuheon Lee , Sunghwan Jang
IPC: G09G5/10
Abstract: Provided are an image display device and a method of operating the same. The image display device includes a backlight unit configured to emit light towards a display panel. The image display device includes an illuminance sensor configured to obtain illuminance information associated with an area that is external to the image display device. The image display device includes a memory configured to store one or more instructions, and a processor configured to execute the one or more instructions stored in the memory to identify a plurality of backlight control patterns, select a backlight control pattern based on the illuminance information, identify brightness information of a current frame, and adjust the brightness of the backlight unit based on the selected backlight control pattern and the brightness information of the current frame.
-
公开(公告)号:US20250069846A1
公开(公告)日:2025-02-27
申请号:US18584633
申请日:2024-02-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Solhee IN , Dohyung Kim , Sungsoo Kim , Jaesup Lee , Byungwook Jung
IPC: H01J37/244 , H01J37/32 , H02J50/20 , H02J50/40 , H02J50/90
Abstract: A system includes a radio frequency (RF) device outputting an RF signal; and at least one sensor device generating a power supply voltage using the RF signal output from the RF device, and operating by the power supply voltage, wherein the sensor device includes a case; a plurality of detectors disposed in the case, and collecting environmental data of a space in which the RF device and the sensor device are input, to generate detection data; a battery supplying a power supply voltage necessary for operation of the plurality of detectors; and a charger charging the battery, wherein the charger includes an antenna installed in the case and receiving RF power from an external source, an RF-DC converter converting an alternating current voltage corresponding to the RF power into a direct current voltage, a matching circuit connected between the antenna and the RF-DC converter, and a DC-DC converter adjusting a level of the direct current voltage and charging the battery.
-
公开(公告)号:US12185450B2
公开(公告)日:2024-12-31
申请号:US18628152
申请日:2024-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dohyung Kim , Seongchul Hong , Insung Kim , Jinhong Park , Jungchul Lee
IPC: H05G2/00 , G03F7/00 , H01L21/268
Abstract: Disclosed are semiconductor manufacturing apparatuses and operating methods thereof. The semiconductor manufacturing apparatus includes an oscillation unit that includes a first seed laser, a second seed laser, and a seed module, wherein the first seed laser oscillates a first pulse, and wherein the second seed laser oscillates a second pulse, and an extreme ultraviolet generation unit configured to use the first and second pulses to generate extreme ultraviolet light. The seed module includes a plurality of mirrors configured to allow the first and second pulses to travel along first and second paths, respectively, and a pulse control optical system including a first optical element, a second optical element, and a third optical element. The pulse control optical system is on the second path that does not overlap the first path. The third optical element includes a lens between the first optical element and the second optical element.
-
10.
公开(公告)号:US20240176230A1
公开(公告)日:2024-05-30
申请号:US18462796
申请日:2023-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hachul Shin , Dohyung Kim , Jooon Park , Sanghwan Lee , Seongchul Hong
IPC: G03F1/70
CPC classification number: G03F1/70
Abstract: There is provided an extreme ultraviolet (EUV) overlay correcting method capable of effectively correcting an overlay error in an EUV exposure process and a method of manufacturing a semiconductor device including the same. The EUV overlay correcting method includes forming a first photoresist (PR) pattern on a wafer by performing an EUV exposure process using a reticle, inspecting an EUV overlay for the first PR pattern and obtaining a first overlay for a first overlay parameter in which an overlay three-dimensionally increases away from a center to opposing sides of the first PR pattern in a first direction perpendicular to a scan direction, calculating deformation data of the reticle based on the first overlay, applying a voltage to a clamp electrode of a reticle stage to create the reticle into a deformed reticle, and forming a second PR pattern on the wafer by performing an EUV exposure process using the deformed reticle.
-
-
-
-
-
-
-
-
-