公开(公告)号：US20220172775A1

公开(公告)日：2022-06-02

申请号：US17510828

申请日：2021-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyoon PARK ,  Sungwon Yun ,  Hyunjun Yoon ,  Wontaeck Jung

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A method of operating a memory device that performs a plurality of program loops for a plurality of memory cells includes applying a first program pulse and a first verify pulse of a first program loop from among the plurality of program loops, counting a first off cell count by using an output based on the first verify pulse, determining a first verify skip period using the first off cell count, applying an N-th program pulse and a plurality of verify pulses in response to an end of the first verify skip period, counting a second off cell count by using an output based on the plurality of verify pulses, and determining a second verify skip period using the second off cell count.

公开(公告)号：US20220013178A1

公开(公告)日：2022-01-13

申请号：US17199062

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Yang ,  Wontaeck Jung

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: In a method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are disposed in a vertical direction in each memory block. An erase loop is performed once or more on an entire of a first memory block in the one or more memory blocks. After the erase loop is successfully completed, a first partial verification operation is performed on one or more groups of a plurality of groups in the first memory block. After the first partial verification operation is successfully completed, it is determined whether a second partial verification operation is required for a group of the one or more groups. The second partial verification operation is performed on one or more subgroups of a plurality of subgroups in a first group requiring the second partial verification operation among the plurality of groups.

公开(公告)号：US20230333782A1

公开(公告)日：2023-10-19

申请号：US18340950

申请日：2023-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wontaeck Jung ,  Bohchang Kim ,  Kuihan Ko ,  Jaeyong Jeong

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0655 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H10B43/27

Abstract: A memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and operate any one of different control schemes for each of the first memory blocks based on a number of first not-open (N/O) strings included in each of the first memory blocks, respectively.

公开(公告)号：US11726722B2

公开(公告)日：2023-08-15

申请号：US17307317

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wontaeck Jung ,  Bohchang Kim ,  Kuihan Ko ,  Jaeyong Jeong

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H10B43/27

CPC classification number: G06F3/0679 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0655 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  H10B43/27

Abstract: A memory system includes a first memory device including a plurality of first memory blocks each including a plurality of first memory cells stacked in a direction perpendicular to a substrate; and a memory controller configured to control a memory operation of the first memory device. The memory controller is configured to select and operate any one of different control schemes for each of the first memory blocks based on a number of first not-open (N/O) strings included in each of the first memory blocks, respectively.

公开(公告)号：US11894092B2

公开(公告)日：2024-02-06

申请号：US17325690

申请日：2021-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myoungho Son ,  Wontaeck Jung ,  Buil Nam

IPC: G11C29/50 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  H01L25/065 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C29/50004 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/349 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  G11C2029/5004 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

公开(公告)号：US11763901B2

公开(公告)日：2023-09-19

申请号：US17397012

申请日：2021-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungnam Lee ,  Daehan Kim ,  Wontaeck Jung

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/28 ,  G11C16/3409

Abstract: A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells.

公开(公告)号：US11380403B2

公开(公告)日：2022-07-05

申请号：US17199062

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu Yang ,  Wontaeck Jung

IPC: G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L27/11582

Abstract: In a method of erasing data in a nonvolatile memory device including one or more memory blocks, a plurality of memory cells are disposed in a vertical direction in each memory block. An erase loop is performed once or more on an entire of a first memory block in the one or more memory blocks. After the erase loop is successfully completed, a first partial verification operation is performed on one or more groups of a plurality of groups in the first memory block. After the first partial verification operation is successfully completed, it is determined whether a second partial verification operation is required for a group of the one or more groups. The second partial verification operation is performed on one or more subgroups of a plurality of subgroups in a first group requiring the second partial verification operation among the plurality of groups.

公开(公告)号：US12230343B2

公开(公告)日：2025-02-18

申请号：US17324787

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bohchang Kim ,  Wontaeck Jung ,  Kuihan Ko ,  Jaeyong Jeong

IPC: G11C29/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device including: a memory cell array including a plurality of memory cells forming a plurality of strings in a vertical direction with a substrate; and a control logic configured to detect a not-open string (N/O string) from the plurality of strings in response to a write command and convert pieces of target data to be programmed on a plurality of target memory cells in the N/O string so that the pieces of target data have a value that limits a number of times a program voltage is applied to the plurality of target memory cells.

公开(公告)号：US12205656B2

公开(公告)日：2025-01-21

申请号：US17881009

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dobin Kim ,  Wontaeck Jung ,  Jaehyuk Yang ,  Jinwoo Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device and a method for programming the same may include, applying program loops to a plurality of memory cells of the memory device to adjust threshold voltages of the plurality of memory cells to desired target states, each of the program loops including a program section and a verification section, programming the memory cells of a first page, storing a number of first program loops used to complete the programming of the memory cells of the first page to a first target state, programming the memory cells of a second page to the first target state, the second page adjacent to the first page, and performing a verification operation on the second page.

公开(公告)号：US20240021255A1

公开(公告)日：2024-01-18

申请号：US18356522

申请日：2023-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myungnam Lee ,  Daehan Kim ,  Wontaeck Jung

IPC: G11C16/34 ,  G11C16/28 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/28 ,  G11C16/16 ,  G11C16/3409

Abstract: A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells.