公开(公告)号：US20210193661A1

公开(公告)日：2021-06-24

申请号：US17032040

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  SATORU YAMADA ,  SUNGWON YOO ,  JAEHO HONG

IPC: H01L27/108 ,  G11C7/18

Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

公开(公告)号：US20220130856A1

公开(公告)日：2022-04-28

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  JAEHO HONG ,  YONGSEOK KIM ,  ILGWEON KIM ,  HYEOUNGWON SEO ,  SUNGWON YOO ,  KYUNGHWAN LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L25/065 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

公开(公告)号：US20200258905A1

公开(公告)日：2020-08-13

申请号：US16856663

申请日：2020-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  BYOUNG-TAEK KIM ,  TAE HUN KIM ,  DONGKYUN SEO ,  JUNHEE LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US20240244847A1

公开(公告)日：2024-07-18

申请号：US18243726

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  JEON IL LEE ,  DAEWON HA

IPC: H10B51/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L23/5283 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: A semiconductor device may include first stacks and second stacks, which are alternately disposed on a substrate in a first direction parallel to a top surface of the substrate, and first pads and second pads connecting the first stacks to the second stacks. Each of the first and second stacks may include a gate electrode, channel patterns, which enclose a side surface of the gate electrode and are spaced apart from each other, and first and second conductive lines connected to a corresponding channel pattern. The first and second conductive lines of the second stack may be disposed to be adjacent to the first and second conductive lines, respectively, of the first stack. The first and second pads may be connected to the first and second conductive lines, respectively, of the first and second stacks.

公开(公告)号：US20230115434A1

公开(公告)日：2023-04-13

申请号：US17868944

申请日：2022-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  JONGMAN PARK ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/11507

Abstract: Disclosed is a semiconductor memory device including a substrate, a plurality of source lines extending in a first direction on the substrate, a plurality of word lines crossing the source lines and extending in a second direction different from the first direction, a plurality of bit lines crossing the source lines and the word lines and extending in a third direction different from the first direction and the second direction, and a plurality of memory cells disposed at intersections between the source lines, the word lines, and the bit lines. The first, second, and third directions are parallel to a top surface of the substrate.

公开(公告)号：US20220367514A1

公开(公告)日：2022-11-17

申请号：US17671533

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  SUNGWON YOO ,  KYUNGHWAN LEE ,  JAEHO HONG

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A semiconductor memory device may include a stack including word lines and interlayer insulating patterns alternatingly stacked on a substrate, the word lines being extended in a first direction parallel to a top surface of the substrate, semiconductor patterns crossing the word lines and having a long axis extended in a second direction parallel to the top surface of the substrate, data storage patterns respectively interposed between the semiconductor patterns and the word lines, the data storage patterns including a ferroelectric material, bit lines extended in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, each of the bit lines being in contact with first side surfaces of the semiconductor patterns spaced apart from each other in the third direction, and a source line in contact with second side surfaces of the semiconductor patterns.

公开(公告)号：US20190139983A1

公开(公告)日：2019-05-09

申请号：US16168219

申请日：2018-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  BYOUNG-TAEK KIM ,  TAE HUN KIM ,  DONGKYUN SEO ,  JUNHEE LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US20230397430A1

公开(公告)日：2023-12-07

申请号：US18303854

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KISEOK LEE ,  KEUNNAM KIM ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  KYUNGHWAN LEE

IPC: H10B51/30 ,  H10B51/20

CPC classification number: H10B51/30 ,  H10B51/20

Abstract: A semiconductor memory device includes a first channel pattern and a second channel pattern stacked on a substrate, a word line disposed between the first and second channel patterns and that extends in a first direction parallel to a top surface of the substrate, a data storage pattern disposed between a top surface of the word line and the first channel pattern and between a bottom surface of the word line and the second channel pattern, a bit line that extends in a second direction perpendicular to the top surface of the substrate and that is connected to first end portions of the first and second channel patterns, and a source line that extends in the second direction and is connected to second end portions of the first and second channel patterns.

公开(公告)号：US20220406797A1

公开(公告)日：2022-12-22

申请号：US17679255

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  KYUNGHWAN LEE

IPC: H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes a plurality of first conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the first direction and second direction being horizontal directions, a plurality of vertical semiconductor patterns disposed on the plurality of first conductive lines, respectively, a gate electrode crossing the plurality of first conductive lines and penetrating each of the plurality of vertical semiconductor patterns, a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns, and a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns.

公开(公告)号：US20210151101A1

公开(公告)日：2021-05-20

申请号：US17036004

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  CHEONAN LEE ,  SATORU YAMADA ,  JUNHEE LIM

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.