公开(公告)号：US20180351080A1

公开(公告)日：2018-12-06

申请号：US16045824

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： JUNG-HOON BAK ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

公开(公告)号：US10109676B2

公开(公告)日：2018-10-23

申请号：US15293771

申请日：2016-10-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hoon Bak ,  Woo-Jin Kim ,  Mina Lee ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/10

Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.

公开(公告)号：US11462679B2

公开(公告)日：2022-10-04

申请号：US17038779

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

公开(公告)号：US10833250B2

公开(公告)日：2020-11-10

申请号：US16045824

申请日：2018-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

公开(公告)号：US09431610B2

公开(公告)日：2016-08-30

申请号：US14868350

申请日：2015-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Yoon-Jong Song ,  Chil-Hee Chung

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.

Abstract translation: 相变存储器件包括相变存储器单元和散热器。 相变存储器单元包括相变材料层图案，被配置为加热相变材料层图案的相变材料层图案下面的下电极和相变材料层图案上的上电极。 散热器被配置成从相变存储器单元吸收热量。 散热器具有比上电极的顶表面低的顶表面，并且与相变存储单元间隔开。