公开(公告)号：US09431610B2

公开(公告)日：2016-08-30

申请号：US14868350

申请日：2015-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Yoon-Jong Song ,  Chil-Hee Chung

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.

Abstract translation: 相变存储器件包括相变存储器单元和散热器。 相变存储器单元包括相变材料层图案，被配置为加热相变材料层图案的相变材料层图案下面的下电极和相变材料层图案上的上电极。 散热器被配置成从相变存储器单元吸收热量。 散热器具有比上电极的顶表面低的顶表面，并且与相变存储单元间隔开。

公开(公告)号：US09634012B2

公开(公告)日：2017-04-25

申请号：US15015651

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

IPC: H01L21/311 ,  H01L27/108 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

公开(公告)号：US09559103B2

公开(公告)日：2017-01-31

申请号：US14716594

申请日：2015-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min Park ,  Tae-Jin Park ,  Yong-Kwan Kim ,  Yoo-Sang Hwang

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894

Abstract: Provided is a memory device. The memory device includes a substrate including a cell area and a peripheral area; gate line stacks and bit line stacks configured to vertically cross in the cell area; buried contacts disposed in areas, which are simultaneously shared by neighboring gate line stacks and neighboring bit line stacks; expanded landing pads including expanded portions connected to the buried contacts and expanded over adjacent bit line stacks, and disposed in a row; landing pads spaced apart from the expanded landing pads as a column, connected to the buried contacts, and having horizontal widths smaller than those of the expanded landing pads; and first storage nodes connected to the expanded portions of the expanded landing pads, and second storage nodes connected to the landing pads.

Abstract translation: 提供了一种存储器件。 存储装置包括：基板，包括单元区域和周边区域; 栅极线堆叠和位线堆叠被配置为在单元区域中垂直交叉; 埋设的触点设置在由相邻栅极线堆叠和相邻位线堆叠同时共享的区域中; 扩展的着陆焊盘，包括连接到埋入触点的扩展部分，并在相邻位线堆叠上扩展，并且布置成一排; 与扩展的着陆焊盘间隔开的着陆焊盘作为柱，连接到埋置的触点，并且具有比扩展的焊盘的水平宽度小的水平宽度; 以及连接到扩展的着陆焊盘的扩展部分的第一存储节点，以及连接到着陆焊盘的第二存储节点。

公开(公告)号：US20170025420A1

公开(公告)日：2017-01-26

申请号：US15015651

申请日：2016-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Jin Park ,  Chan-sic Yoon ,  Ki-Seok Lee ,  Hyeon-Ok Jung ,  Dae-Ik Kim ,  Bong-Soo Kim ,  Yong-Kwan Kim ,  Eun-Jung Kim ,  Se-Myeong Jang ,  Min-su Choi ,  Sung-Hee Han ,  Yoo-Sang Hwang

IPC: H01L27/108 ,  H01L21/308

CPC classification number: H01L27/10894 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885

Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

Abstract translation: 在形成有源图案的方法中，在基板的单元区域上沿第一方向形成第一图案，并且在基板的外围电路区域上形成第二图案。 第一图案沿与第一方向交叉的第三方向延伸。 第一掩模在第一图案上沿第一方向形成，第二掩模形成在第二图案上。 第一掩模沿与第三方向交叉的第四方向延伸。 第三掩模形成在沿第四方向延伸的第一掩模之间。 使用第一至第三掩模蚀刻第一和第二图案以形成第三和第四图案。 使用第三和第四图案蚀刻衬底的上部，以在单元和外围电路区域中形成第一和第二有源图案。