公开(公告)号：US20230276628A1

公开(公告)日：2023-08-31

申请号：US18312782

申请日：2023-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin JUNG ,  Bong Tae PARK ,  Ho Jun SEONG

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

公开(公告)号：US20190035807A1

公开(公告)日：2019-01-31

申请号：US15991476

申请日：2018-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon KIM ,  Young-Jin JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/792

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

公开(公告)号：US20190326317A1

公开(公告)日：2019-10-24

申请号：US16223894

申请日：2018-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin JUNG ,  Sunghan CHO

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L29/423

Abstract: A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.

公开(公告)号：US20190164989A1

公开(公告)日：2019-05-30

申请号：US16122037

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun LEE ,  Jae-Hoon JANG ,  Jae-Duk LEE ,  Joon-Hee LEE ,  Young-Jin JUNG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/308 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/308 ,  H01L21/76837 ,  H01L27/11556 ,  H01L27/11565 ,  H01L29/40117

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US20210343740A1

公开(公告)日：2021-11-04

申请号：US17360013

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin JUNG ,  Bong Tae PARK ,  Ho Jun SEONG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

公开(公告)号：US20210036009A1

公开(公告)日：2021-02-04

申请号：US16818294

申请日：2020-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin JUNG ,  Bong Tae PARK ,  Ho Jun SEONG

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11575 ,  H01L23/522 ,  H01L27/11565

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

公开(公告)号：US20200381453A1

公开(公告)日：2020-12-03

申请号：US16995084

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun LEE ,  Jae-Hoon JANG ,  Jae-Duk LEE ,  Joon-Hee LEE ,  Young-Jin JUNG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L27/11556 ,  H01L21/28

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.